LTPO Array Substrate Layout With Shared Oxide and LTPS Layers
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Solution Overview
Problem
Low temperature polycrystalline oxide (LTPO) technology, which combines the advantages of low temperature polysilicon (LTPS) and oxide technologies, faces challenges due to its complex film layers and high number of mask processes, leading to increased product cost and reduced yield.
Innovation Solution
The array substrate design includes a display area with sub-pixels and a non-display area containing polysilicon transistors, where oxide transistors and pixel electrodes are formed in the same layer, reducing the number of mask processes and simplifying manufacturing, with the active layer of the oxide transistor and pixel electrode being in contact and made of oxide semiconductor and conductor materials respectively, and the gate and electrodes of both transistors in the same layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LTPO substrate design is used, then oxide transistor and polysilicon transistor can be manufactured with separate process routes, but the number of mask processes increases to more than 15, increasing manufacturing complexity and cost
Solution Approach 1:
The patent merges the manufacturing processes of oxide transistors and polysilicon transistors into a unified process flow. Specifically, the gate electrodes of both transistor types are formed in the same mask process, and the source/drain electrodes are formed together in another mask process. This consolidation reduces the total number of mask processes from more than 15 to fewer steps, directly resolving the contradiction between maintaining transistor performance and reducing manufacturing complexity.
Solution Approach 2:
The patent creates universal process steps that serve multiple functions. For example, a single mask process forms both the gate electrode of the oxide transistor and the gate electrode of the polysilicon transistor. Another mask process forms both the source/drain electrodes of the oxide transistor and the source/drain electrodes of the polysilicon transistor. This multi-functionality approach reduces the overall process count while maintaining the performance characteristics of both transistor types.
2Reliability
If separate process routes are used for oxide and polysilicon transistors, then each transistor type can be optimized independently, but the production cost and yield become more difficult to control
Solution Approach 1:
The patent combines the manufacturing processes for oxide and polysilicon transistors into unified process flows. The gate electrodes are formed simultaneously in one mask process, and the source/drain electrodes are formed together in another mask process. This merging reduces the number of process steps, improves yield by reducing cumulative process variations, and lowers production cost through process consolidation, while still allowing each transistor type to maintain its optimized performance characteristics.
3Reliability
If additional electrodes are added to complete the transistor structure, then the transistor functionality is improved, but the aperture ratio and transmittance are reduced
Solution Approach 1:
The patent extracts and eliminates the drain electrode from the oxide transistor structure. By removing this additional electrode, the patent reduces the total area occupied by electrodes in the sub-pixel, thereby increasing the aperture ratio and transmittance. The transistor functionality is maintained through alternative structural arrangements, such as using the source electrode for both transistor operation and as part of the pixel electrode structure, thus resolving the contradiction between transistor functionality and optical performance.
Data Source
AI summary
The present application provides an array substrate, a manufacturing method for the same, and a display panel. The array substrate includes a display area and a non-display area connected to the display area, and the display area includes a plurality of sub-pixels arranged in an array. The non-display area includes at least one polysilicon transistor, each of the sub-pixels includes an oxide transistor and a pixel electrode. A gate of the oxide transistor as well as a first electrode and a second electrode of the polysilicon transistor are arranged in a same layer; an active layer of the oxide transistor and the pixel electrode are arranged in a same layer, and are in contact with each other. The active layer of the oxide transistor includes an oxide semiconductor material, and the pixel electrode includes an oxide conductor material.