3D Ground Plane Mesa Isolation for Lower-Cost Circuit Stacking
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Solution Overview
Problem
The production of 3D integrated circuits with a ground plane layer requires expensive and complex insulation processes, particularly the STI method, which is costly due to planarization steps and high-temperature oxide densification, and limits the thermal budget in producing upper transistor levels.
Innovation Solution
A method involving the formation of islands in the second semiconductor layer, etching distinct portions of the ground plane layer, depositing metal and semiconductor compounds, and forming insulating zones around these areas to create conductive pads, which reduces the number of steps and costs compared to traditional STI processes, and allows for improved silicidation and contact quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If STI (shallow trench insulation) process is used to isolate the ground plane layer, then insulation around active areas and ground plane portions is achieved, but production cost increases due to expensive planarization steps and high-temperature oxide densification
Solution Approach 1:
The patent extracts and eliminates the expensive STI process steps (planarization and high-temperature oxide densification) by replacing them with a simpler isolation method using deposited insulating material that fills the spaces around ground plane portions without requiring these costly processing steps
Solution Approach 2:
The patent changes the processing parameters by eliminating high-temperature densification steps and complex planarization, using instead a deposition-based approach that achieves insulation at lower temperatures and reduced process complexity
2Reliability
If STI process with planarization steps is used, then proper insulation is achieved, but the thermal budget for producing upper transistor levels is limited
Solution Approach 1:
The patent changes the temperature parameters by replacing high-temperature oxide densification steps with lower-temperature deposition processes, thereby preserving thermal budget for subsequent upper transistor level fabrication
3Reliability
If traditional STI process is used for ground plane isolation, then insulation is achieved, but the number of manufacturing steps and process complexity increase
Solution Approach 1:
The patent extracts and removes the complex multi-step STI process (trench formation, dielectric deposition, planarization, oxide densification) and replaces it with a simpler process using deposited insulating material that achieves the same isolation function with fewer steps
Solution Approach 2:
Instead of removing material to create trenches and then filling them (traditional STI), the patent inverts the approach by directly depositing insulating material to form isolation regions, achieving the same result through an opposite process sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces production costs and complexity, enables silicidation over a larger surface area, and produces contacts with improved quality and reduced resistance, while maintaining the thermal budget constraints of 3D circuit production.
Implementation Method 1
one or more zones of a metal-semiconductor composite are formed by depositing at least one metallic layer on the ground plane and at least one region of the first portion, followed by at least one thermal annealing. Thus, silicification is performed before insulation
Implementation Method 2
The material and thickness of this insulating layer are designed to allow for electrostatic coupling between the ground plane and the higher-level semiconductor layer
Implementation Method 3
one or more dielectric materials, such as silicon dioxide, are deposited to fill the trench
Data Source
Figure 1A~1D
Figure 1E~1G
Figure 2~4
AI summary
Implementation of a layered (N1, N2) device comprising, in this order: a) providing on a given level (N1) having one or more components (T11, T12) made at least partially in a first semiconductor layer (11): a stack comprising a second semiconductor layer (36) capable of accommodating at least one transistor channel (T21) of level (N2) higher than said given level (N1), said stack comprising a layer (34) called a ground plane layer made of conductive or doped semiconductor material or material capable of being doped, located between the first semiconductor layer (11) and the second semiconductor layer (36), as well as an insulating layer (35) separating the ground plane layer (34) from the second semiconductor layer (36), one or more islands (36a) being defined in the second semiconductor layer (36), b) forming a gate (42) of a transistor (T21) on at least one islet (36a) among said one or more islets,(c) define by etching distinct portions (34a, 34b) in the second semiconductor layer (34) of the ground plane so as to free up a space (51) around at least one first etched portion (34a) of the ground plane layer disposed under and opposite said island (36a), (d) form an insulating zone around said island (36a) and said first portion (34a) by depositing at least one layer of insulating material (62) covering the grid (42) and said island (36a), the insulating layer (62) filling said space (51) around said first portion (34a) of the ground plane layer.