Pixel Electrode Contact Structure for Low-Resistance Array Substrates
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Solution Overview
Problem
Conventional array substrates for display devices face high contact resistance between the pixel electrode and the drain electrode due to a small contact area, leading to low effective current and high power consumption.
Innovation Solution
The pixel unit design includes a first bottom conductive layer that entirely covers the drain electrode, increasing the contact area and reducing resistance, with additional bottom conductive layers covering the source electrode and data line to prevent electrochemical reactions during etching, allowing for a one-stage patterning process that enhances adhesion and control over etching dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via-hole is used to connect the pixel electrode to the drain electrode, then the connection is achieved, but the contact area is small and contact resistance is high
Solution Approach 1:
The patent transitions from a single-point via-hole connection to a multi-layer stacked conductive structure that extends vertically through multiple planarization layers. This dimensional expansion creates multiple contact interfaces (first bottom conductive layer, second bottom conductive layer, third bottom conductive layer) that collectively provide a much larger effective contact area between the pixel electrode and drain electrode, thereby reducing contact resistance.
Solution Approach 2:
The patent employs a composite conductive structure consisting of multiple conductive layers (bottom conductive layer, middle conductive layer, top conductive layer) with different materials and functions. Each layer serves specific purposes: the bottom conductive layers provide electrical connection and prevent electrochemical reactions, the middle layer provides structural support and additional conduction path, and the top layer forms the pixel electrode. This composite approach optimizes both electrical performance and structural integrity.
2Reliability
If multiple conductive layers are stacked, then contact resistance is reduced and effective current increases, but power consumption increases
Solution Approach 1:
The patent optimizes the electrical parameters of the conductive layers by carefully selecting material compositions, layer thicknesses, and resistivities. The bottom conductive layers use materials with appropriate resistivity to balance conduction efficiency and electrochemical stability. By precisely controlling these parameters, the structure achieves low contact resistance and high effective current while minimizing unnecessary power consumption through optimized electrical characteristics.
3Reliability
If bottom conductive layers cover the source electrode and data line, then electrochemical reactions during etching are prevented, but the structure becomes more complex
Solution Approach 1:
The bottom conductive layers serve multiple functions simultaneously: (1) providing electrical connection between conductive layers, (2) preventing electrochemical reactions during etching processes by acting as protective barriers, (3) serving as adhesion layers to enhance bonding between different structural layers, and (4) functioning as part of the overall conductive path. This multi-functionality reduces the need for separate protective layers, thereby managing structural complexity while achieving reliable defect prevention.
4Productivity
If a one-stage patterning process is used, then manufacturing efficiency is improved, but control over etching dimensions becomes more difficult
Solution Approach 1:
The patent incorporates preliminary protective measures in the form of bottom conductive layers that are deposited before the etching process. These layers pre-establish protective barriers and adhesion interfaces that remain intact during the one-stage patterning process. By preparing these protective structures in advance, the patent enables aggressive one-stage etching to proceed without compromising dimensional control or causing electrochemical damage to the underlying structures.
Data Source
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AI summary
Pixel unit, array substrate, and display device, and their fabrication methods are provided. The disclosed pixel unit can include: a transistor (2), including a drain electrode (21); a pixel electrode (3), including a first bottom conductive layer (311) in contact with a surface of the drain electrode (21) and a metal layer (32); and a planarization layer (4), formed on the transistor (2) and the first bottom conductive layer (311). The metal layer (32) is electrically connected to the first bottom conductive layer (311) through a via-hole in the planarization layer (4).