Field Plate Biasing Layout for High-Voltage Gate-Drain Stress
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High voltage semiconductor devices face challenges in managing electrical field stress between the gate and drain, leading to inefficiencies and potential gate overload, particularly in off-states due to the large voltage differences.
Innovation Solution
An integrated circuit design incorporating multiple field plates between the gate and drain, coupled with a biasing circuit comprising high voltage depletion mode transistors and resistors, which provide independent and increasing biasing voltages to each field plate based on distance from the gate, thereby relieving electric field stress and creating a flatter field profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large length is provided between the gate and drain to handle high voltage electrical fields, then the device can handle high voltages in the off state, but the device complexity and area increase
Solution Approach 1:
The patent divides the single gate-drain region into multiple segments by introducing intermediate field plates (first and second field plates) between the gate and drain. Each field plate is independently biased to create separate electrical field zones, allowing the device to handle high voltages without requiring an excessively long gate-drain distance. This segmentation enables high voltage handling while maintaining a compact device structure.
2Object-affected harmful factors
If a large length is provided between the gate and drain to handle high voltage, then the electrical field stress is reduced, but the device area and manufacturing complexity increase
Solution Approach 1:
The patent introduces intermediate field plates as mediator structures between the gate and drain. These field plates are biased at intermediate voltages (first field plate at first bias voltage, second field plate at second bias voltage) to gradually transition the electrical potential, thereby reducing electrical field stress without requiring a large gate-drain distance. The intermediaries distribute the voltage stress across multiple smaller field regions.
3Stability of the object's composition
If multiple field plates are introduced to linearize the field profile, then the field distribution is improved, but the device complexity and number of components increase
Solution Approach 1:
The patent applies local quality by providing different bias voltages to different field plates based on their positions. The first field plate receives a first bias voltage and the second field plate receives a second bias voltage, creating locally optimized electrical field conditions in each region. This local customization of field conditions achieves overall field profile linearization while using a manageable number of field plates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency of high voltage semiconductor devices by reducing leakage current and maintaining a stable field profile across the device, improving performance and reliability.
Implementation Method 1
The biasing circuit includes a plurality of high voltage depletion mode transistors, each having a pinch off voltage
Implementation Method 2
each having a different pinch-off voltage based on a distance of the respective field plate from the gate
Implementation Method 3
a set of resistors, each coupled between a source of the semiconductor device and a respective high voltage depletion mode transistor
Implementation Method 4
the length between the gate and drain must be large enough to handle the electrical fields in both the on and off states
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.