Buried Gate Structure With FD-SOI Isolation for BCAT Coupling Control
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Solution Overview
Problem
As integrated circuit devices with buried channel array transistors (BCATs) experience increased integration and reduced design rules, the narrow line widths of buried word lines lead to electrical coupling and disturbance phenomena, complicating the formation and uniformity of buried channel transistors.
Innovation Solution
The implementation of a fully depleted silicon on insulator (FD-SOI) structure isolates the gate structure from the substrate, and a semiconductor channel structure layer is formed on each buried word line to reduce electrical coupling and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased and design rules are reduced, then the integration density is improved, but the line widths of buried word lines become narrower causing electrical coupling and disturbance phenomena
Solution Approach 1:
The patent divides the continuous substrate into isolated regions by introducing element isolation films between adjacent buried word lines. This segmentation prevents electrical coupling between neighboring word lines, allowing narrow line widths to be used without causing disturbance phenomena, thus enabling high integration while maintaining electrical performance stability.
Solution Approach 2:
The element isolation film acts as an intermediary insulating layer positioned between adjacent buried word lines. This intermediate structure blocks electrical field coupling and current leakage between neighboring word lines, resolving the electrical coupling issue that arises from reduced line widths in high-density integration.
2Productivity
If the line widths of buried word lines are reduced, then the integration capacity is improved, but the formation and uniformity of buried channel transistors become more difficult
Solution Approach 1:
By segmenting the substrate with element isolation films, each buried word line operates as an independent transistor unit with well-defined boundaries. This segmentation simplifies the formation process and improves uniformity, as the isolation films provide clear lateral confinement for the channel region, making it easier to achieve consistent transistor characteristics even with narrow line widths.
Solution Approach 2:
The element isolation films create locally distinct regions with different electrical properties - insulating regions between word lines and active conducting regions within each transistor. This local differentiation of electrical characteristics enables precise control over current flow and transistor formation, improving manufacturing precision for narrow-line-width devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high integration, high reliability, and improved electrical performance by blocking electron and hole movement with the outer insulating layer, reducing disturbance phenomena and ensuring uniform electrical characteristics.
Implementation Method 1
an outer insulating layer conformed along an inner wall of the gate trench... blocking electron and hole movement with the outer insulating layer
Data Source
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AI summary
An integrated circuit device includes a substrate including an element isolation film defining an active area, and a gate structure buried in the active area of the substrate. The gate structure includes a gate trench, an outer insulating layer conformed along an inner wall of the gate trench, a channel structure layer conformed on the outer insulating layer, a gate insulating layer conformed on the channel structure layer, a gate electrode layer filling a lower area of the gate trench, and a capping insulating layer on the gate electrode layer, the capping insulating layer filling an upper area of the gate trench.