3D Memory Cell Strings With Selective Void Formation
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming memory cells with optimal electrical coupling and void space management, leading to potential shorting and reduced performance in memory arrays.
Innovation Solution
A method involving a vertical stack of alternating insulative and conductive tiers above a conductor tier, where channel-material strings electrically couple with the conductor tier, and sacrificial material is selectively etched to create void space between conductive tiers, preventing shorting and optimizing memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sacrificial material is etched in memory-cell region, then void spaces are formed between conductive tiers, but selective etching relative to insulating material is challenging
Solution Approach 1:
The patent applies local quality by making the insulating material have different etch resistance properties in different regions. Specifically, the insulating material is configured to have greater etch resistance than the sacrificial material, enabling selective removal of sacrificial material while preserving insulating material during the etching process. This local differentiation of material properties solves the selective etching challenge.
2Reliability
If void spaces are maximized between conductive tiers, then short circuits are prevented, but structural integrity may be compromised
Solution Approach 1:
The patent applies local quality by creating void spaces selectively in memory-cell regions while maintaining solid insulating material in non-memory-cell regions (such as wordline regions). This localized void formation prevents short circuits in memory cells while the remaining solid insulating material maintains overall structural integrity of the stacked conductor-insulator system.
3Productivity
If selective etching is performed to form void spaces, then memory cell performance is optimized, but manufacturing process complexity increases
Solution Approach 1:
The patent applies parameter changes by configuring the insulating material to have different etch resistance parameters compared to the sacrificial material. This parameter differentiation (etch resistance) enables the etching process to selectively remove sacrificial material while leaving insulating material intact, optimizing memory cell performance through controlled void formation without requiring excessively complex manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes void space between conductive tiers, reduces shorting risks, and enhances the performance and reliability of memory arrays by ensuring direct electrical coupling and efficient electrical isolation.
Implementation Method 1
The sacrificial material in the memory-cell region is etched selectively relative to the insulating, insulator, or insulative material of the at least one of the (a), (b), or (c), respectively, to form void space between immediately-adjacent of the conductive tiers in the memory-cell region and to not form void space between the at least two conductive tiers of said at least one of the (a), (b), or (c).
Data Source
AI summary
A memory array comprising strings of memory cells comprises a vertical stack comprising vertically-alternating insulative tiers and conductive tiers directly above a conductor tier. Channel-material-string constructions of memory-cell strings extend through the insulative and conductive tiers. The channel material of the channel-material-string constructions directly electrically couples with conductor material of the conductor tier. The vertical stack comprising a memory-cell region comprises memory cells. Individual of the insulative tiers in the memory-cell region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being void space. The vertical stack comprises an upper region directly above the memory-cell region. The upper region comprises at least two of the conductive tiers and that comprise upper select gates Individual of the insulative tiers in the upper region laterally-outward of the channel-material-string constructions have at least a majority of their insulative matter being solid. Other embodiments, including method, are disclosed.