Dual-Gate Transistor Arrays for Low-Voltage RRAM Access
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Solution Overview
Problem
The scalability of resistive random-access memory devices is limited by the voltage and drive current requirements of field-effect transistors, restricting the ability to shrink their dimensions.
Innovation Solution
A structure comprising a dielectric layer on a substrate with pairs of field-effect transistors, where each pair includes a semiconductor layer connected to the other, positioned between gate electrodes, allowing for independent biasing and reduced voltage requirements through shared gate electrodes and wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If field-effect transistors are shrunk to improve scalability, then device density increases, but voltage and drive current requirements cannot be met
Solution Approach 1:
The transistor gate is segmented into two independent gates (first gate electrode and second gate electrode) that can be controlled separately. This segmentation allows independent optimization of voltage control and drive current, enabling smaller transistor dimensions while maintaining sufficient drive current through coordinated gating.
Solution Approach 2:
The invention changes the electrical parameters by introducing dual gate control with different voltage potentials. By independently adjusting the voltage on each gate, the transistor can achieve the required drive current at lower operating voltages, thus enabling scaling to smaller dimensions while meeting power requirements.
2Use of energy by moving object
If operating voltage is reduced to enable scaling, then power consumption decreases, but drive current requirements cannot be met
Solution Approach 1:
The gate is divided into two independently controllable gate electrodes. This segmentation enables one gate to provide the necessary drive current while the other gate controls the operating voltage, allowing simultaneous satisfaction of both drive current and low voltage requirements for scaled devices.
Solution Approach 2:
The dual gate structure enables dynamic control where the voltage and drive current can be independently adjusted through separate gate potentials. This dynamic control allows the transistor to operate at reduced voltages while still delivering the required drive current through optimized gate biasing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reduced operating voltages for accessing resistive memory elements, enhancing scalability and operational efficiency of resistive random-access memory devices.
Implementation Method 1
A well may be formed in the substrate by introducing a dopant by ion implantation
Data Source
Figure 1~2
Figure 2A~3
Figure 3A~4
AI summary
Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.