HBM Buffer Die Interfaces for Higher Bandwidth Without Larger Controllers
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Solution Overview
Problem
High-bandwidth memory (HBM) systems face challenges in increasing computational and memory capabilities for data-intensive applications like machine learning, leading to a need for more physical interfaces, which in turn increases the chip area of the memory controller, limiting performance without area expansion.
Innovation Solution
A memory device with a buffer die containing two interface circuits that can be selectively activated by different voltage levels, allowing multiple memory dies to communicate with a single memory controller, thereby enabling high-speed and high-performance operations without expanding the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple physical interfaces are added to support high-capacity memory operations, then memory bandwidth and computational capability are improved, but chip area of the memory controller increases
Solution Approach 1:
The patent merges multiple physical interfaces into a single shared interface. The memory device includes a first physical interface and a second physical interface that share a common communication channel with the memory controller. By time-division multiplexing or selective activation of interfaces, the system achieves high-bandwidth memory operations without requiring separate dedicated physical interfaces for each memory stack, thus avoiding proportional increases in chip area.
Solution Approach 2:
The memory controller is designed with universal interface capability that can handle multiple memory stacks through a single physical interface. The interface is configured to support multiple memory devices by dynamically allocating communication resources, allowing one physical interface to serve multiple memory stacks sequentially or in parallel modes, eliminating the need for dedicated interfaces for each stack.
2Adaptability or versatility
If the number of PHYs in the memory controller is increased to support multiple memory stacks, then communication capability with memory devices is improved, but device complexity increases
Solution Approach 1:
The patent segments the communication function into logical channels within a single physical interface. Instead of implementing multiple complete PHYs, the system divides the single interface into multiple logical communication channels that can be independently controlled and allocated to different memory stacks, reducing hardware complexity while maintaining multi-stack communication capability.
Solution Approach 2:
The interface configuration is made dynamic rather than static. The memory controller can dynamically activate or deactivate specific interface circuits based on which memory stack needs communication at any given time. This dynamic allocation allows the system to adapt communication resources to current needs without maintaining permanently active multiple complex interface circuits.
Data Source
AI summary
A memory device and a system includes a plurality of physical interfaces. The memory device includes a buffer die including a first interface circuit and a second interface circuit configured to communicate with an external device and a memory die stack mounted on the buffer die and including a plurality of stacked memory dies. The plurality of memory dies are electrically connected to the first interface circuit and the second interface circuit, the first interface circuit is configured to activate responsive to a first selection signal, and the second interface circuit is configured to activate responsive to a second selection signal. The first selection signal and the second selection signal are received from a memory controller external to the memory device.