Stress Buffer Layer Structure for Low-Leakage IC Dielectrics

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Solution Overview

Problem

Highly integrated integrated circuit devices face challenges in achieving optimal dielectric layer characteristics due to thermal expansion coefficient mismatches, leading to increased leakage currents and poor electrical performance.

Innovation Solution

Incorporating a first stress buffer layer between the electrode layer and dielectric layer, formed by thermal stress, and optionally a second stress buffer layer, to reduce lattice mismatch and improve dielectric layer characteristics, using metal oxides with specific thermal expansion coefficients and crystal structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a dielectric layer is formed directly on the electrode layer, then the device structure is simple, but thermal expansion coefficient mismatch causes lattice mismatch and increases leakage current

Engineering Contradiction:
Improvedevice structureVSAvoidleakage current
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

A stress buffer layer comprising a metal oxide is introduced between the dielectric layer and the electrode layer. This intermediary layer has a thermal expansion coefficient that matches the dielectric layer, thereby reducing lattice mismatch and minimizing leakage current at the interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The thermal expansion coefficient parameter is optimized by selecting a metal oxide material for the stress buffer layer that closely matches the dielectric layer's thermal expansion coefficient. This parameter matching reduces thermal stress and lattice mismatch during temperature variations.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a stress buffer layer is added between the electrode layer and dielectric layer, then leakage current is reduced, but the device structure becomes more complex

Engineering Contradiction:
Improveleakage currentVSAvoiddevice structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stress buffer layer acts as a mediator that resolves the interface compatibility issue between the dielectric layer and electrode layer. By placing this thin intermediary layer, leakage current is significantly reduced while the overall structural complexity remains manageable.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The stress buffer layer utilizes composite material design, specifically a metal oxide layer that combines appropriate thermal expansion properties with good interface compatibility, achieving both reliability improvement and controlled complexity.

Inventive Principle:
Principle #40Composite materials

3Ease of manufacture

If metal oxides with mismatched thermal expansion coefficients are used, then manufacturing is easier, but lattice mismatch increases and dielectric layer characteristics deteriorate

Engineering Contradiction:
Improvemanufacturing processVSAvoidlattice mismatch
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The thermal expansion coefficient of the stress buffer layer is specifically selected to match the dielectric layer. This parameter optimization ensures minimal lattice mismatch while maintaining compatibility with standard manufacturing processes for metal oxide deposition.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stress buffer layers effectively reduce leakage currents and enhance the dielectric layer's performance by minimizing lattice mismatch and improving capacitance characteristics.

Implementation Method 1

a first stress buffer layer between the first electrode layer and the dielectric layer, the first stress buffer layer including a first metal oxide including the first metal, and being formed due to thermal stress of the first electrode layer and thermal stress of the dielectric layer

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS11784213B2Integrated circuit device
Publication Date: 2023.10.10 SAMSUNG ELECTRONICS CO LTD
  • US11784213B2 patent drawing
  • US11784213B2 patent drawing
  • US11784213B2 patent drawing

AI summary

An integrated circuit device including a first electrode layer including a first metal and having a first thermal expansion coefficient; a dielectric layer on the first electrode layer, the dielectric layer including a second metal oxide including a second metal that is different from the first metal, and having a second thermal expansion coefficient that is less than the first thermal expansion coefficient; and a first stress buffer layer between the first electrode layer and the dielectric layer, the first stress buffer layer including a first metal oxide including the first metal, and being formed due to thermal stress of the first electrode layer and thermal stress of the dielectric layer.