Stepped-Gate e-Mode HEMT Structure to Prevent Gate Degradation
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Solution Overview
Problem
Current enhancement mode high electron mobility transistors (HEMTs) suffer from reliability issues due to gate degradation caused by implant isolation region formation during processing, leading to charge buildup and potential current paths around the gate.
Innovation Solution
A semiconductor structure with a barrier layer having a thick portion laterally between thin portions and a gate with a semiconductor layer and gate conductor layer, where the gate has stepped opposing end walls and thin barrier layer portions minimize charge buildup, potentially eliminating the need for implant isolation regions, and if necessary, these regions can be shallow and offset from the gate to prevent current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If implant isolation regions are formed during processing, then current paths around the gate are blocked, but gate degradation occurs and reliability decreases
Solution Approach 1:
The patent removes the gate conductor layer at the ends of the gate, extracting the problematic portion that extends over the barrier layer. This eliminates the charge buildup mechanism that causes gate degradation while maintaining the isolation function through modified barrier layer geometry alone.
Solution Approach 2:
The barrier layer is designed with non-uniform thickness, featuring thicker portions at the ends and thinner portions in the middle. This local variation in barrier layer quality prevents charge buildup at critical locations without requiring complete removal of isolation structures, thereby protecting the gate while maintaining current blocking functionality.
2Reliability
If deep implant isolation regions are formed, then current paths are blocked, but manufacturing complexity and processing depth increase
Solution Approach 1:
The patent eliminates the need for deep implant isolation regions by removing the gate conductor layer at the ends and relying on the modified barrier layer structure to provide sufficient isolation. This simplifies the device structure by removing unnecessary deep isolation features.
Solution Approach 2:
The patent changes the geometric parameters of the barrier layer (thickness variation) to achieve isolation functionality without requiring deep implantation. By adjusting the barrier layer thickness profile, effective isolation is achieved with shallower or no implant isolation regions, reducing manufacturing complexity.
3Reliability
If the gate conductor layer extends over the barrier layer, then gate coverage is complete, but charge buildup occurs leading to reliability issues
Solution Approach 1:
The gate conductor layer is selectively removed at the ends of the gate where it would otherwise extend over the barrier layer. This extraction prevents charge buildup at these critical locations while maintaining adequate gate conductor coverage over the active channel region for proper device operation.
Solution Approach 2:
The gate conductor layer is present in some regions (over the channel) but absent in others (at the ends over the barrier layer). This spatially varying gate conductor structure prevents charge buildup at problematic locations while maintaining operational functionality where the conductor is needed.
Data Source
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AI summary
A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer (103) with a thick portion (103T) positioned laterally between thin portions (103t) and a gate. The gate includes a semiconductor layer (132) (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion (132T) positioned laterally between thin portions (132t). The gate also includes a gate conductor layer (133) on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.