TFT Source Region Layout for Higher Display Pixel Density
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Solution Overview
Problem
Current electronic devices face challenges in meeting the increasing demand for higher resolution due to process limitations in their display technology.
Innovation Solution
The design includes a substrate with data and gate lines, featuring thin film transistors with semiconductor structures that have a channel region, source region, and drain region, where the source region is electrically connected to the data line and forms an acute angle with it, allowing for a closer arrangement of transistors without yield reduction, thereby improving resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the source region is arranged perpendicular to the data line in conventional designs, then the layout is simple and easy to manufacture, but the arrangement density of thin film transistors is limited and resolution cannot be improved
Solution Approach 1:
The source region is designed to extend in a direction forming an acute angle (e.g., 45 degrees) with the data line, breaking the conventional perpendicular symmetry. This asymmetric arrangement allows transistors to be packed more densely along the data line direction while maintaining proper electrical connections, thereby increasing the arrangement density without compromising manufacturing feasibility
Solution Approach 2:
Instead of arranging the source region solely along the vertical direction (perpendicular to data line), the invention introduces a diagonal dimension by extending the source region at an acute angle. This dimensional change enables more efficient space utilization and higher transistor density while keeping the layout relatively simple for manufacturing
2Manufacturing precision
If transistors are arranged closer together to improve resolution, then the display resolution increases, but the risk of short circuits and yield reduction increases
Solution Approach 1:
The drain region is designed with a specific geometry where it extends in a first direction and has a second direction component, creating a localized structural quality that maintains adequate spacing between adjacent transistors. This local structural optimization ensures proper electrical isolation and reduces short circuit risk while enabling closer overall transistor arrangement for higher resolution
Solution Approach 2:
The semiconductor structure is divided into distinct regions (channel region, source region, drain region) with specific geometric configurations. The drain region's segmented design with extended portions in different directions creates natural spacing and isolation between adjacent transistors, reducing the risk of short circuits while allowing higher density arrangement
Data Source
AI summary
An electronic device is provided. The electronic device includes a substrate, a data line and a gate line that are disposed on the substrate. The data line extends in a first direction. The electronic device also includes a thin film transistor. The thin film transistor is disposed on the substrate and includes a semiconductor structure. The semiconductor structure includes a channel region, a source region, and a drain region. The gate line overlaps the channel region. The source region is electrically connected to the data line. The source region and the drain region are located on opposite sides of the gate line. The source region includes a first portion extending in a second direction, and an acute angle is formed between the first direction and the second direction.