DRAM Capacitor Array Layout for Sacrificial Layer Etching
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Solution Overview
Problem
In the fabrication of dynamic random-access memory (DRAM) capacitors, the challenge is to maintain high storage capacitance while decreasing cell area, as existing etching processes can damage bottom electrode layers during the removal of sacrificial layers, thereby reducing capacitance.
Innovation Solution
A method for forming a capacitor array with a capacitor pattern-dense region and a capacitor pattern-sparse region, where openings for removing the sacrificial layer are formed in the sparse region to prevent damage to the bottom electrode layers, allowing for increased capacitance by avoiding etching above the capacitor contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If etching is performed to remove the sacrificial layer through openings above the capacitor contacts, then the sacrificial layer can be removed, but the bottom electrode layer is damaged during the etching process
Solution Approach 1:
The capacitor array is divided into two distinct regions: a capacitor pattern-dense region where capacitors are formed, and a capacitor pattern-sparse region where the sacrificial layer is removed. This spatial segmentation allows the etching process to be confined to the sparse region, preventing damage to the bottom electrode layer in the dense region while still enabling sacrificial layer removal.
Solution Approach 2:
Different regions of the capacitor array are assigned different functions: the capacitor pattern-dense region maintains intact bottom electrode layers for capacitance storage, while the capacitor pattern-sparse region serves as a sacrificial layer removal zone. This local differentiation enables selective etching that preserves critical structures where needed.
2Area of stationary object
If cell area is decreased to increase memory cell density, then more cells can be packed, but storage capacitance becomes insufficient
Solution Approach 1:
The invention transitions from planar capacitor structures to three-dimensional stacked capacitor structures. By stacking multiple capacitor layers vertically, the storage capacitance is increased without proportionally increasing the cell area, thereby maintaining high memory cell density while achieving sufficient total capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the capacitance of the capacitors by preventing damage to the bottom electrode layers during the etching process, thereby improving storage capacitance without compromising cell area.
Implementation Method 1
etching the second nitride layer and the oxide layer is performed by a dry etching process
Implementation Method 2
removing the oxide layer is performed by a wet etching process; the wet etching process is performed to etch the oxide layer at a faster etch rate than it etches the first and second nitride layers
Implementation Method 3
removing the mask layer is performed by a planarization process
Data Source
AI summary
A method for forming a capacitor array includes depositing a first nitride layer, a first oxide layer, and a second nitride layer in sequence over first and second contacts on a substrate; etching the first nitride layer, the first oxide layer, and the second nitride layer to form first and second openings exposing the first and second contacts; conformally depositing a bottom electrode layer over the first and second nitride layers and the first oxide layer and on the first and second contacts; etching the second nitride layer and the first oxide layer to form a third opening having a bottom position higher than a top surface of the first nitride layer; removing the first oxide layer through the third opening; forming a capacitor dielectric layer over the bottom electrode layer; forming a top electrode layer over the capacitor dielectric layer.