Single-Layer Silicon Nitride Spacer for 1.5T SONOS Memory
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Solution Overview
Problem
The fabrication of current 1.5T SONOS memory devices is complex and results in a large chip area occupancy due to the need for multiple spacer layers and the inter-poly oxide layer deposition process.
Innovation Solution
A semiconductor memory device with a simplified structure featuring single-layer dielectric spacers and a gap filling layer, where the spacers and gap filling layer are composed of a single silicon nitride layer, eliminating the need for multiple spacer layers and the inter-poly oxide layer deposition process, and using atomic layer deposition for conformal coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple spacer layers and inter-poly oxide layer are deposited, then insulation between gates is improved, but fabrication complexity increases and chip area occupancy increases
Solution Approach 1:
The patent combines multiple separate dielectric layers (inter-poly oxide layer and multiple spacer layers) into a single integrated gap filling layer formed by conformal deposition. This merging reduces the number of deposition steps and simplifies the fabrication process while maintaining the insulation function between the memory gate and control gate.
Solution Approach 2:
The gap filling layer serves multiple functions simultaneously: it provides insulation between gates, acts as a spacer structure, and defines the geometric relationship between gates. This multi-functionality eliminates the need for separate dedicated spacer layers and inter-poly oxide layers, reducing fabrication complexity.
2Reliability
If multiple spacer layers are formed, then gate insulation is improved, but chip area occupancy increases
Solution Approach 1:
The patent merges multiple spacer layers into a single gap filling layer that is conformally deposited in the gap region between gates. This consolidation reduces the vertical stack height and minimizes the chip area occupied by spacer structures while preserving the insulation function.
Solution Approach 2:
The invention transitions from forming spacer layers that extend vertically above the gate surfaces to a gap filling approach that confines the dielectric material primarily within the horizontal gap region between gates. This dimensional change reduces the vertical footprint and chip area occupancy.
3Reliability
If inter-poly oxide layer deposition is performed, then gate insulation is improved, but fabrication process complexity increases
Solution Approach 1:
The patent combines the inter-poly oxide layer deposition with spacer formation into a single conformal gap filling deposition step. This eliminates the need for separate inter-poly oxide deposition, patterning, and etching steps, significantly simplifying the fabrication process while maintaining gate insulation.
Solution Approach 2:
The invention extracts and eliminates the unnecessary inter-poly oxide layer deposition step from the fabrication process by integrating its insulation function into the gap filling layer formation. This removal of redundant steps reduces fabrication complexity without compromising device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces chip area occupancy, and lowers production costs by eliminating unnecessary steps and spacer layers, while maintaining effective insulation and doping regions.
Implementation Method 1
using atomic layer deposition for conformal coverage
Data Source
AI summary
A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.