3D Semiconductor Memory Device Etch Barrier Design
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited due to the high cost of fine pattern formation equipment, necessitating the development of three-dimensional structures to enhance performance and reduce costs.
Innovation Solution
A semiconductor memory device with a three-dimensional structure is manufactured using a stack with alternating dielectric and electrode layers, where dummy channels act as an etch barrier to simplify the process and reduce defects, allowing for the selective removal of sacrificial layers within the coupling region while maintaining them inside the coupling region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional structure is adopted to increase integration, then productivity and cost-effectiveness are improved, but device complexity increases
Solution Approach 1:
The substrate is divided into distinct regions: a cell region containing memory cells and a coupling region for peripheral circuits. This spatial segmentation allows different functional areas to be optimized independently, enabling high integration through 3D stacking while managing complexity through regional specialization.
Solution Approach 2:
Different regions of the device have different structural characteristics. The cell region uses a uniform alternating stack of first and second dielectric layers throughout, while the coupling region selectively removes second dielectric layers to create electrode spaces. This local differentiation optimizes each region for its specific function while maintaining overall integration.
2Manufacturing precision
If separate etch barrier formation steps are added to protect coupling region dielectric layers, then manufacturing precision is improved, but device complexity and manufacturing time increase
Solution Approach 1:
The second dielectric layers serve multiple functions: they act as sacrificial layers during fabrication to define electrode spaces, and simultaneously serve as functional dielectric layers in the final device structure. This multi-functionality eliminates the need for separate etch barrier layers, reducing process complexity while maintaining manufacturing precision through selective removal.
Solution Approach 2:
The second dielectric layers are pre-positioned in alternating stacks throughout the device before any etching occurs. Their strategic placement allows them to automatically function as etch barriers during subsequent selective removal processes, eliminating the need for additional barrier formation steps and simplifying the manufacturing process.
3Manufacturing precision
If multiple manufacturing steps are used to form different dielectric structures in cell and coupling regions, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The alternating stack of first and second dielectric layers is formed uniformly across the entire substrate before any regional differentiation. This preliminary uniform formation simplifies the early manufacturing process, and subsequent selective removal of second dielectric layers in the coupling region achieves the required structural differentiation without adding excessive process complexity.
Solution Approach 2:
The second dielectric layers in the coupling region are temporarily removed to create electrode spaces, but the first dielectric layers remain intact. This selective discarding approach allows efficient formation of different regional structures from a uniform initial stack, improving productivity by avoiding multiple separate formation processes while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces defects, and lowers costs by eliminating separate etch barrier formation steps, thereby improving yield and reducing manufacturing time and expenses.
Implementation Method 1
removing the second dielectric layers by using the plurality of dummy channels as an etch barrier such that the plurality of second dielectric layers inside the coupling region remain and the plurality of second dielectric layers outside the coupling region are removed
Data Source
AI summary
A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.