Transistor TRIZ Cases

Post metal annealing on a capping layer reduces gate leakage and capacitance equivalent thickness without interfacial regrowth.

A switching element driving circuit uses a pull-down resistor to discharge parasitic capacitances at the control terminal.

Dummy deep trenches in logic regions stabilize trench etch processes, ensuring uniform profiles and minimizing leakage variations in adjacent eDRAM devices.

A segmented contact structure with nested collar and plug components increases the effective electrical connection area in finFET transistors.

Oxidizing dummy gates forms protective layers preventing CMP over-polishing and metal residue short circuits in PMOS devices.

V-shaped pixel electrodes reduce color chromaticity variation across wide viewing angles while maintaining high resolution.

A metal oxide film protects the channel in an oxide semiconductor transistor to suppress charge trapping at the interface.

A shared plug couples gate electrodes to back gates, increasing ON current while reducing leakage and simplifying double gate complexity.

Diagonal conductive via paths form a truss structure that prevents laminate warping and delamination during thermal excursions.

Diffusing oxygen from an insulating layer into a metal contact reduces Schottky barrier height and signal propagation delays.

Internal low breakdown voltage switch controls external high breakdown voltage switch via cascode configuration.

In-situ epitaxial doping replaces ion implantation to reduce leakage currents and dark current degradation while maintaining uniform dopant distribution.

Reflective metallization layers deflect LED radiation away from driver circuits to prevent absorption and ensure reliability.

Selective precursor deposition forms conformal crystalline source and drain contacts on semiconductor devices.

Flat bottom spacers eliminate concave meniscus shapes at source/drain junctions, ensuring uniform effective gate length and reducing device variability.

Longitudinal offset of electrical contact pads reduces overlapping area to lower OFF-state capacitance while maintaining low ON-state resistance.

Buried dummy gate structures in area isolation layers maintain structural integrity and reduce process deviations during device scaling.

Selective etching depths and epitaxial growth enable concurrent fabrication of horizontal gate-all-around transistors with varying nanowire channel densities.

An overlying conductive contact connects a trench capacitor to a drain junction through interlevel dielectric.

Chlorine-based etching removes III-V features from high aspect ratio fins while integrated chamber abatement prevents arsenic contamination.

Two-stage contact holes reduce aspect ratio to eliminate voids, ensuring reliable electrical properties and fast write recovery time.

A non-volatile memory cell uses a conductive spacer as a floating gate to reduce transistor size.

Concave structures in the substrate allow dielectric and metal layers to fill recesses, resolving the contradiction between chip integration and capacitance.

Recessing sacrificial layers in a nanosheet FET creates dielectric spacers that isolate channels, reducing leakage current and threshold voltage.

A flash memory gate stack uses segmented dielectric and conductive layers to increase facing area.

An amorphous silicon light absorbing layer prevents laser energy from damaging metal oxide semiconductor active layers during flexible substrate stripping.

An anti-fuse cell structure uses distinct gate dielectric thicknesses for reading and programming devices to enable controlled breakdown.

Overlapping capacitors with power supply lines widens the light-emitting region, resolving the trade-off between aperture ratio and manufacturing complexity.

Segmented partial vias reduce series resistance and extend the 3 dB cut-off frequency of on-die capacitors while avoiding complex power grid re-routing.

Varying doping concentrations in a buried layer reduce resistance and increase holding voltage to shrink the device footprint.

Protruding gate structures compensate for manufacturing misalignment between stacked transistors, maintaining reliable electrostatic coupling integrity.

A continuous high-k dielectric film extends across adjacent transistor channel regions to unify the gate stack structure.

Fin-shaped and pillar-shaped semiconductor layers with metal gate lines reduce cell area while allowing source lines at different levels than bit lines.

Asymmetrical contact holes in a static electricity blocking circuit prevent short circuits while discharging charge to power lines.

Gate lines share adjacent zones between pixels to reduce light-shielding block area and increase aperture ratio.

Light ion implantation modifies dielectric layers to enable selective hydrofluoric acid etching, preventing silicon consumption and spacer feet defects.

A dual-cell OTP ROM structure segments programming functions to independently rupture oxide layers using breakdown voltage coupling.

A printed circuit board assembly with internally configurable dual switch areas and drivers provides flexible disconnection capabilities.

Dual transistor overvoltage protection circuit eliminates external diodes, reducing power loss from reverse polarity events and saving chip space.

Self-aligned source formation via insulating film thickness variation reduces gate electrode pitch and on-resistance in vertical gate devices.

Localized Joule heating enables selective deposition of sensing materials on nanodevice regions during chemical vapor deposition.

Front-end-of-line metal-insulator-metal capacitor structure integrates with transistor fabrication to reduce resistance loads.

Two-step etching creates a recessed trench gate to reduce channel length variation and gate-drain capacitance.

A buffer structure uses trapezoidal grooves to form capillary channels that hold organic material.

Segmenting the gate electrode creates two parasitic capacitors whose combined invariable total capacitance withstands photolithographic vibration deviations.

Concentric circular source and drain electrodes reduce parasitic capacitance and leakage current in liquid crystal display devices.

A tiled power module positions a chip vertically alongside a passive element to reduce current impedance.

A semiconductor device uses a stacked capacitor structure with light-transmitting conductive films to increase charge capacitance.