Thin Film Transistor Gate Electrode Extension for Parasitic Capacitance Stability
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Solution Overview
Problem
The manufacturing process of thin film transistor liquid crystal display panels is prone to deviations due to machine vibration during photolithographic exposure, leading to variations in the parasitic capacitor between the gate and drain electrodes, causing feed-through voltage fluctuations and issues like mura and flicker in liquid crystal display panels.
Innovation Solution
A thin film transistor structure is designed with a gate electrode and a gate electrode portion, an insulating layer, and an amorphous silicon layer, where the drain electrode partially overlaps both, forming two parasitic capacitors with equal variance, maintaining a constant total capacitance to stabilize the voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithographic exposure is performed with standard drain electrode configuration, then manufacturing process is simple, but machine vibration causes drain electrode location deviation leading to parasitic capacitor variation
Solution Approach 1:
The gate electrode is segmented into two parts: the main gate electrode and the gate electrode portion (extension). This segmentation allows the gate electrode portion to specifically compensate for drain electrode location deviations while the main gate electrode maintains its primary function, thus resolving the contradiction between manufacturing simplicity and location precision.
Solution Approach 2:
The gate electrode portion is designed in advance to overlap with the amorphous silicon layer in a specific configuration. This preliminary structural arrangement ensures that even when the drain electrode location deviates due to machine vibration, the parasitic capacitor variation is compensated, maintaining manufacturing precision without complicating the photolithographic process.
2Adaptability or versatility
If drain electrode location varies due to machine vibration, then manufacturing process is tolerant, but parasitic capacitor varies causing feed-through voltage fluctuation
Solution Approach 1:
The gate electrode portion is designed to provide preliminary anti-action against the harmful effect of drain electrode location deviation. By pre-configuring the gate electrode portion to overlap with the amorphous silicon layer, the structure compensates for parasitic capacitor variations before they affect pixel performance, thus maintaining reliability while tolerating manufacturing variations.
Solution Approach 2:
The invention converts the harmful effect of drain electrode location deviation into a beneficial compensation mechanism. The gate electrode portion, positioned to overlap with the amorphous silicon layer, creates a compensatory parasitic capacitor that offsets the variation caused by drain electrode misalignment, thus converting manufacturing tolerance into a reliability-enhancing feature.
3Reliability
If gate electrode portion is added to compensate for deviation, then parasitic capacitor stability improves, but device structure becomes more complex
Solution Approach 1:
The gate electrode portion is merged with the existing gate electrode structure, forming an integrated gate electrode assembly. This merging approach allows the compensation function to be achieved without adding a completely separate component, thus improving parasitic capacitor stability while minimizing the increase in device complexity.
Solution Approach 2:
The gate electrode portion serves multiple functions: it compensates for drain electrode location deviations, maintains parasitic capacitor stability, and integrates with the existing gate electrode structure. This multi-functionality reduces the need for additional components, thereby improving reliability without significantly increasing device complexity.
Data Source
AI summary
A thin film transistor structure of a pixel is provided. In the present invention, a first metal layer serves as a gate electrode, and the gate electrode includes an extending gate electrode portion. A second metal layer includes a drain electrode partially and respectively overlapping the gate electrode and the gate electrode portion with the amorphous silicon layer interposed therebetween so as to form a first parasitic capacitor and a second parasitic capacitor. The total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable to withstand deviation caused by vibration of the machine in the photolithographic process, so that undesired effects in the liquid crystal display panel such as mura and flicker can be reduced.


