Anti-fuse Cell With Differential Gate Dielectric Thickness
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Solution Overview
Problem
Existing anti-fuse memory technologies face challenges in efficiently programming and reading states without reverse-engineering, as the programming states of anti-fuse cells cannot be determined through reverse engineering, and there is a need for a structure that simplifies the operation and reduces the size of anti-fuse cells while maintaining the reverse-engineering proof feature.
Innovation Solution
The proposed solution involves an anti-fuse cell structure with a reading device (R_MOS) and a programming device (MOS_Cap or Pro_MOS) connected to the same word-line, where the gate dielectrics have different thicknesses, allowing for controlled breakdown during programming without affecting the reading device, and sharing a common active region and P_well region to reduce cell size and simplify operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate dielectric thickness is reduced to enable programming, then the programming capability is improved, but the reading device reliability deteriorates
Solution Approach 1:
The patent applies local quality by implementing different gate dielectric thicknesses in different locations within the same cell structure. The programming device has a thinner gate dielectric (first thickness) to enable breakdown and programming, while the reading device has a thicker gate dielectric (second thickness greater than the first) to maintain reliability during read operations. This spatial differentiation of dielectric thickness allows simultaneous optimization of programming capability and reading reliability within a unified cell architecture.
2Reliability
If separate structures are used for reading and programming devices, then the operational reliability is improved, but the cell size increases
Solution Approach 1:
The patent merges the reading device and programming device into a single integrated cell structure. Both devices share common components including the active region, source/drain regions, and control gates, while maintaining distinct gate dielectric layers with different thicknesses. This consolidation reduces the overall cell footprint and simplifies the cell architecture compared to using completely separate structures, while the differentiated dielectric thicknesses ensure that reading and programming operations can be performed reliably without interfering with each other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of programming and reading operations, reduces cell size, and maintains the reverse-engineering proof feature by ensuring the reading device remains unbroken during programming, allowing for effective state determination and simplified control circuits.
Implementation Method 1
the gate dielectrics of MOS capacitors/transistors may be broken down to cause the gate and the source/drain regions of a programming capacitor/transistor to be interconnected
Data Source
AI summary
A structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode connected to the word-line, a first gate dielectric underlying the first gate electrode, a drain region connected to the bit-line, and a source region. The first gate dielectric has a first thickness. The drain region and the source region are on opposite sides of the first gate electrode. The anti-fuse cell further includes a programming device including a second gate electrode connected to the word-line, and a second gate dielectric underlying the second gate electrode. The second gate dielectric has a second thickness smaller than the first thickness. The programming device further includes a source/drain region connected to the source region of the reading device.