Surrounding Gate Transistor NAND Circuit Area Reduction
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Solution Overview
Problem
The increasing scale of semiconductor integrated circuits, particularly in leading-edge micro-processing units, requires more efficient transistor designs to minimize area and reduce the need for body terminals, which are wasteful in planar transistors.
Innovation Solution
The use of surrounding gate transistors (SGTs) arranged in a line on a substrate, with silicon pillars and insulators, eliminates the need for body terminals by connecting source, drain, and gate hierarchically perpendicular to the substrate, allowing for a compact and efficient layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar transistors are used with complete isolation between n-well and p-type substrate, then transistor reliability is improved, but device area increases due to required body terminals
Solution Approach 1:
The patent transitions from planar transistor architecture to three-dimensional surrounding gate transistor architecture. The gate electrode wraps around the semiconductor layer in multiple directions (surrounding gate structure), moving from two-dimensional planar layout to three-dimensional spatial arrangement. This dimensional change enables better control of the semiconductor layer while reducing the footprint area required for each transistor, directly addressing the contradiction between reliability and area.
Solution Approach 2:
The surrounding gate structure implements a nested configuration where the gate electrode is positioned around and adjacent to the semiconductor layer, with the gate insulating film nested between them. The source and drain regions are nested within the semiconductor layer structure. This nested arrangement maximizes the control effect of the gate while minimizing the overall device area, resolving the contradiction between achieving reliable transistor operation and reducing area.
2Area of stationary object
If surrounding gate transistors are arranged in a line, then area efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into multiple identical transistor units arranged in a linear array. Each transistor unit consists of segmented components: semiconductor layer portion, gate insulating film portion, gate electrode portion, source region, and drain region. This segmentation into repeating modular units simplifies the manufacturing process by enabling standardized fabrication steps that can be applied uniformly across all transistors, reducing overall manufacturing complexity despite the advanced three-dimensional structure.
Solution Approach 2:
The surrounding gate transistor structure serves multiple functions simultaneously: the gate electrode provides electrical control, the gate insulating film provides electrical isolation, and the three-dimensional arrangement provides both area efficiency and control over the semiconductor layer. This multi-functional design achieves area efficiency while maintaining manufacturing feasibility through universal fabrication processes.
Data Source
AI summary
A semiconductor device includes a two-input NAND circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NAND circuit having a small area.