Recessed Gate Word Line Formation for DRAM Alignment
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Solution Overview
Problem
Conventional methods for forming transistor and bit line contacts in semiconductor devices require multiple photolithography processes, leading to misalignment issues and increased fabrication costs, particularly as DRAM dimensions shrink, resulting in shorts between bit line contacts and word lines.
Innovation Solution
A method involving recessed gates and deep trench capacitor devices with spacers and buried conductive portions to form parallel shallow trenches, allowing for the creation of word lines with narrower widths that overlap recessed gates, reducing the space occupied by word lines and improving bit line contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography processes are used to form transistor and bit line contact, then the fabrication process can be completed, but misalignment occurs among the four photolithography processes and fabrication costs increase
Solution Approach 1:
The patent combines the formation of transistor gates and bit line contacts into a single photolithography process. The word line pattern is used as a mask to simultaneously define both the transistor gates and the bit line contact regions, reducing the number of separate photolithography steps from four to two while improving alignment precision.
Solution Approach 2:
The word line pattern serves multiple functions: it acts as the functional word line for memory operations, serves as a mask for defining transistor gates, and defines the bit line contact regions. This multi-functionality eliminates the need for separate patterning steps for each feature.
2Reliability
If the determined width of the word line is used, then the word line can be formed, but it occupies space for the bit line contact causing shorts and contact failures
Solution Approach 1:
The word line width is varied locally: it has a first width in regions where it overlaps with recessed gates, and a narrower second width in regions where it would otherwise occupy bit line contact space. This local variation ensures proper electrical isolation while maintaining word line functionality in gate regions.
Solution Approach 2:
The word line is segmented into different width portions along its length. The patterned word line creates distinct regions: wider portions for gate overlap and narrower portions for bit line contact areas, effectively segmenting the conductive path to prevent shorts.
3Productivity
If DRAM dimensions are shrunk to increase density, then storage capacity increases, but shorts between bit line contact and word line become increasingly serious
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional recessed gate structures. By forming gates that extend vertically into recesses in the substrate, the design separates the word line and bit line contact in the vertical dimension while maintaining horizontal integration, preventing shorts even as dimensions shrink.
Solution Approach 2:
The recessed gate structure nests the gate within a recess in the substrate, with the word line forming over the recessed gate. The bit line contact is formed in a separate recess adjacent to the gate recess. This nested arrangement allows closer spacing while maintaining electrical isolation through the substrate material.
Data Source
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AI summary
A method for forming a semiconductor device. A substrate (100) is provided, wherein the substrate has recessed gates (118) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions (104) and the protrusions. Buried portions of conductive material (134a,b) are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches (132) for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions (134a) serve as buried bit line contacts. Word lines (140) are formed across the recessed gates (120), wherein at least one of the word lines comprises portions overlapping the recessed gates. At least one of the overlapped portions has a narrower width than at least one of the recessed gates.