Asymmetrical Split-Gate Memory Cell Design
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Solution Overview
Problem
Conventional non-volatile memory cells with split-gate designs face challenges such as increased transistor size, reduced packing density, and complex fabrication processes due to the need for significant source junction overlap and deep substrate implants, which elevate costs and complicate manufacturing.
Innovation Solution
The proposed solution involves forming non-volatile memory cells with an asymmetrical split-gate design where the floating gate is created as a 'stringer' or 'spacer' using a conductive material deposited over the control gate, eliminating the need for deep source junctions and special fabrication features, and employing standard CMOS processes for efficient and cost-effective production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If significant source junction overlap with floating gate and deep substrate implants are used, then high voltage tolerance is achieved, but transistor size increases and packing density decreases
Solution Approach 1:
The patent employs asymmetrical gate structures where the control gate and floating gate have different geometries and positions. The control gate is positioned to provide adequate overlap with the source junction for high voltage tolerance, while the floating gate is optimized for charge storage. This asymmetrical arrangement allows the transistor to achieve high voltage tolerance without requiring excessive overall transistor dimensions, thereby improving packing density while maintaining reliability.
2Reliability
If special fabrication features such as thick oxide layers and buried high-voltage source junctions are implemented, then device performance is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent designs the control gate structure to serve multiple functions: it provides voltage control for the channel, ensures adequate overlap with the source junction for high voltage tolerance, and works in conjunction with the floating gate for charge storage. By making the control gate multi-functional, the patent eliminates the need for separate buried high-voltage source junctions and special thick oxide layers, thereby simplifying the fabrication process while maintaining device performance.
Solution Approach 2:
The patent optimizes the geometric parameters of the control gate and floating gate, such as their lengths, widths, and spacing, to achieve the desired electrical characteristics. By carefully adjusting these parameters, the patent achieves high voltage tolerance and proper charge storage functionality using standard oxide thicknesses and conventional fabrication processes, avoiding the need for special fabrication features and reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of memory cells, increases packing density, and simplifies the fabrication process, enabling low-voltage, low-power operation with high efficiency and compatibility with standard CMOS processes, while maintaining performance comparable to split-gate flash memory.
Implementation Method 1
a stringer or spacer (floating gate) is formed using a conductive material deposited over the control gate
Data Source
AI summary
A method includes forming at least one control gate over a semiconductor substrate. The method also includes depositing a layer of conductive material over the at least one control gate and the semiconductor substrate. The method further includes etching the layer of conductive material to form multiple spacers adjacent to the at least one control gate, where at least one of the spacers forms a floating gate in at least one memory cell. Two spacers could be formed adjacent to the at least one control gate, and one of the spacers could be etched so that a single memory cell includes the control gate and the remaining spacer. Also, two spacers could be formed adjacent to the at least one control gate, and the at least one control gate could be etched and separated to form multiple control gates associated with different memory cells.