Thin Film Transistor Gate Projection for Short Channel Effect
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Solution Overview
Problem
As display resolution increases, the size of transistors in display panels decreases, leading to a short channel effect that negatively impacts the electrical properties and performance of the display panel, particularly due to the increased influence of the gate on the heavily doped regions.
Innovation Solution
A thin film transistor design featuring a channel region with heavily doped semiconductor patterns on both sides, a second semiconductor pattern, a gate insulating layer, and source and drain patterns, where the gate pattern's projection is within the channel region's projection on the substrate, and a buffer layer is optionally included to mitigate the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the transistor size is reduced to increase display resolution, then the display resolution is improved, but the short channel effect becomes more obvious and electrical properties deteriorate
Solution Approach 1:
The transistor structure is segmented into multiple functional regions: channel region, heavily doped first semiconductor pattern, and second semiconductor pattern. This segmentation allows each region to perform its specific function optimally, with the channel region maintaining electrical performance while the doped regions provide necessary doping without excessive gate influence.
Solution Approach 2:
Different regions of the transistor are given different doping concentrations and material properties. The channel region maintains appropriate doping for electrical performance, while the first semiconductor pattern is heavily doped to provide contact regions. The second semiconductor pattern adds local quality enhancement to suppress the short channel effect without affecting the entire transistor uniformly.
2Length of moving object
If the channel length is shortened to reduce transistor size, then the transistor size is reduced, but the gate's influence on the heavily doped region increases and performance deteriorates
Solution Approach 1:
The transistor is divided into distinct segments: a channel region with controlled length, heavily doped first semiconductor patterns at the contacts, and a second semiconductor pattern bridging them. This segmentation allows the channel length to be shortened for miniaturization while the heavily doped regions maintain electrical performance through localized high doping concentrations.
Solution Approach 2:
The doping concentration parameter is changed locally in different regions. The first semiconductor pattern uses heavy doping to provide low-resistance contacts, while the channel region uses lighter doping to maintain mobility. The second semiconductor pattern introduces additional local doping to counteract the short channel effect, allowing short channel lengths without performance degradation.
Data Source
AI summary
The present disclosure provides a thin film transistor, a fabricating method thereof, an array substrate, and a display device. The thin film transistor includes: a substrate; a channel region; a heavily doped first semiconductor pattern located on both sides of the channel region; a second semiconductor pattern disposed on the heavily doped first semiconductor pattern; a gate insulating layer covering the channel region and the second semiconductor pattern; a gate pattern disposed on the gate insulating layer, an orthographic projection of the gate pattern on the substrate being within an orthographic projection of the channel region on the substrate; and a source pattern and a drain pattern in contact with the heavily doped first semiconductor pattern through the first via and the second via, respectively.