Partial Vias in Metal-Insulator-Metal Capacitors for High-Frequency Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The design of metal-insulator-metal (MiM) capacitors in semiconductor dies faces challenges in achieving high-frequency capacitance due to limited space for vias and increased series resistance, which restricts the effective capacitance and 3 dB cut-off frequency, especially as die size decreases and switching frequency increases.
Innovation Solution
The implementation of partial vias, which connect only to internal layers and do not extend through the entire die, allows for increased capacitance at higher frequencies without re-routing power grid layers, reducing equivalent resistive components and extending the frequency range of MiM capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias are used to connect MiM plates to adjacent grid layers, then electrical connections are established, but series resistance increases and high-frequency capacitance is limited
Solution Approach 1:
The patent divides the single through via into multiple partial vias that connect to different power grid layers at different heights. This segmentation reduces the length of each individual via path, thereby reducing the series resistance of each connection while maintaining reliable electrical connection through multiple distributed paths.
Solution Approach 2:
The patent transitions from a single vertical dimension connection (through via) to a multi-dimensional connection structure where partial vias connect at different heights and locations. This dimensional approach allows connections to be distributed across multiple power grid layers, reducing the effective resistance by creating parallel current paths.
2Productivity
If die size decreases and switching frequency increases, then integration density improves, but space for vias is limited and series resistance increases
Solution Approach 1:
The patent segments the via structure into multiple partial vias distributed across different power grid layers. This allows the via space to be distributed rather than concentrated, enabling integration density to improve while maintaining sufficient via space through strategic placement across multiple layers.
Solution Approach 2:
The patent utilizes the vertical dimension by creating partial vias at different heights connecting to different power grid layers. This multi-dimensional approach increases the effective via space available without increasing the horizontal die area, thereby maintaining integration density while providing adequate via space.
3Reliability
If power grid layers are re-routed to accommodate more vias, then capacitance at higher frequencies can be increased, but design complexity and manufacturing cost increase
Solution Approach 1:
Instead of re-routing power grid layers to accommodate vias, the patent inverts the approach by allowing partial vias to connect to existing power grid layers at different heights. This eliminates the need to re-route power grid layers while still achieving increased high-frequency capacitance through multiple connection points.
Solution Approach 2:
The patent adds the vertical dimension to via connections by creating partial vias at different heights rather than relying solely on horizontal re-routing. This multi-dimensional connection approach increases high-frequency capacitance without requiring changes to the horizontal power grid routing layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the high-frequency characteristics of MiM capacitors by increasing the 3 dB cut-off frequency and providing better performance without the added cost and complexity of re-routing power grid layers, allowing for more precise capacitor design and improved noise filtering.
Implementation Method 1
A capacitor structure includes a first metal plate in a first metal layer of the die between the power grid layers, a second metal plate in a second metal layer of the die between the first metal plate and the second power grid layer, and a dielectric between the first metal plate and the first power grid layer, and between the second metal plate and the second power grid layer
Data Source
AI summary
A Metal-Insulator-Metal on-die capacitor is described with partial vias. In one example, first and second power grid layers are formed in a semiconductor die. The power grid layers have power rails. First and second metal plates are formed in metal layers of the die between the power grid layers. Full vias extend from a power rail of the first polarity of the first power grid layer to a first side of the second metal plate and from a second side of the second metal plate opposite the first side of the metal plate to a power rail of the first polarity of the second power grid layer. Partial vias extend from the power rail of the first polarity of the second power grid layer and end at the second side of the second metal plate.