Stacked MOS Transistor Electrostatic Coupling via Protruding Gate
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Solution Overview
Problem
Integrated circuits with superimposed MOS transistors face challenges in achieving reliable electrostatic coupling due to misalignment issues during production, which affects the alignment between the gate of the lower transistor and the channel of the upper transistor, leading to difficulties in polarizing the channel effectively.
Innovation Solution
The integration circuit design includes a first MOS-type transistor with a second MOS-type transistor stacked on top, featuring a channel region with approximately parallel primary faces and an electrically conductive material portion connected to the gate of the first transistor, positioned between the gate and the channel of the second transistor, ensuring electrostatic coupling even with misalignment, using a dielectric layer between the conductive material and the channel, and the conductive material's dimensions are larger than the channel region to accommodate alignment uncertainties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate production and assembly of transistor levels is used, then manufacturing flexibility is improved, but alignment precision deteriorates (alignment in vicinity of 100 nm)
Solution Approach 1:
The invention divides the transistor structure into two separate levels that can be produced independently and then assembled. The first level includes the first transistor, and the second level includes the second transistor. This segmentation allows each level to be manufactured separately with optimized processes, while the alignment is subsequently ensured through the protruding gate structure that compensates for alignment tolerances.
2Manufacturing precision
If sequential production of transistor levels is used, then alignment precision is improved (alignment uncertainty about 40% of minimum gate length), but manufacturing complexity increases
Solution Approach 1:
The gate of the first transistor is deliberately designed to protrude beyond the active zone before the second transistor is formed. This preliminary structural action creates a built-in alignment reference that simplifies the subsequent manufacturing process, allowing the second transistor to be aligned relative to the protruding gate without requiring extremely precise alignment processes.
3Reliability
If gate and channel alignment is made critical for electrostatic coupling, then coupling effectiveness is improved, but tolerance to misalignment deteriorates
Solution Approach 1:
The invention changes the geometric parameters of the first transistor's gate, making it protrude beyond the active zone by a specific distance. This parameter change transforms the coupling mechanism from one requiring precise alignment to one that is tolerant of misalignment, as the protruding gate ensures overlapping sections exist even when alignment is imperfect.
Solution Approach 2:
The protruding gate structure acts as a cushion against alignment errors. By anticipating potential misalignment during manufacturing, the design incorporates extra gate material that extends beyond the nominal alignment position, thereby cushioning or compensating for the expected alignment variations and ensuring reliable electrostatic coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures robust electrostatic coupling between superimposed MOS transistors, tolerating misalignment during production, and allows for efficient polarization of the channel, enhancing integration density and performance by using a conductive material with specific dimensions and dielectric layers to maintain coupling integrity.
Implementation Method 1
the gate 17a of the lower transistor 3a can serve to polarize the channel 13b of the upper transistor 3b, in particular owing to the small thickness of the dielectric layer 5
Implementation Method 2
a portion 117 of at least one electrically conductive material electrically connected to a gate 113a of the lower transistor 101a and arranged between said gate 113a and the channel region 109b of the upper transistor
Data Source
AI summary
An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.