Flash Memory Gate Stack Capacitance via Segmented Dielectrics
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Solution Overview
Problem
Existing flash memory devices face challenges in enhancing capacitance between the control gate and the floating gate, which limits their switching performance.
Innovation Solution
A flash memory device structure is developed, featuring a gate stack with multiple dielectric and conductive layers, including a first gate dielectric layer, a conductive layer, a second gate dielectric layer, and a second conductive layer, which increases the facing area between the control gate and the floating gate, thereby enhancing capacitance and switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate stack structure is used, then the device structure is simple, but the capacitance between control gate and floating gate is insufficient, limiting switching performance
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a first gate dielectric layer (Al2O3) between the floating gate and channel, a second gate dielectric layer (HfO2) between the control gate and floating gate, and conductive layers for floating gate and control gate. This segmentation allows each layer to be optimized for its specific function, increasing overall capacitance while maintaining manageable complexity
Solution Approach 2:
The patent employs composite material structure with different dielectric materials (Al2O3 and HfO2) having different permittivity values. The combination of these materials with different electrical properties creates a multi-layer gate dielectric structure that achieves higher effective capacitance than single-material structures, directly addressing the switching performance requirement
2Reliability
If the facing area of the capacitor is increased, then the capacitance increases and switching performance improves, but the device area increases
Solution Approach 1:
The patent extends the capacitor facing area into the vertical dimension by creating a three-dimensional gate stack structure with multiple stacked dielectric and conductive layers. This vertical stacking allows increased capacitance without proportionally increasing the planar device area, as the additional capacitance is achieved through added vertical layers rather than lateral expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased capacitance and facing area between the control gate and floating gate result in improved switching performance and reduced gate resistance, enhancing the overall performance of the flash memory device.
Implementation Method 1
two capacitors connected in serial are formed by arranging dielectric layers between a control gate, a floating gate, and a substrate, such that charges can be kept on the floating gate
Implementation Method 2
a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer; a second gate dielectric layer covering a surface of the first conductive layer
Data Source
AI summary
A flash memory device includes a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, in which the gate stack includes a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second gate dielectric layer. A method for manufacturing a flash memory device disclosed herein.