Stack-Type Capacitor With Concave Substrate For High Integration
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Solution Overview
Problem
As semiconductor devices become more integrated and smaller, it is challenging to maintain high capacitance in capacitors, leading to reduced chip area and potential errors in data storage due to decreased capacitance.
Innovation Solution
The design incorporates a conductive substrate with concave structures covered by dielectric and metal layers, allowing for increased surface area and capacitance, with multiple capacitor structures stacked and electrically connected in parallel to enhance integration and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of the chip decreases to increase integration, then the available chip area for capacitor plate is reduced, but the capacitance of the capacitor is consequently reduced
Solution Approach 1:
The patent transitions from a two-dimensional planar capacitor structure to a three-dimensional structure by forming concave portions in the substrate and filling them with dielectric and metal layers. This vertical dimensionality change allows the capacitor to achieve higher capacitance within a reduced chip area, effectively resolving the contradiction between integration and capacitance.
Solution Approach 2:
The patent embeds the dielectric layer and metal layer within the concave portions of the substrate, creating a nested structure where the capacitor components are housed inside the recesses. This nesting approach maximizes the use of available space, allowing high capacitance to be achieved without increasing the chip footprint.
2Area of stationary object
If the area of capacitor plate is reduced to fit smaller chip size, then integration increases, but the capacitance value decreases leading to data storage errors
Solution Approach 1:
By utilizing the vertical dimension through concave structures, the patent maintains sufficient capacitance value for reliable data storage while reducing the horizontal chip area. The three-dimensional configuration ensures that even with smaller plate area, the capacitance remains adequate for preventing data storage errors.
Solution Approach 2:
The patent applies different properties to different regions by creating concave portions with specific depths and configurations in strategic locations. This local optimization allows the capacitor to achieve the required capacitance density in specific areas while maintaining overall small chip size and high reliability.
Data Source
AI summary
A capacitor structure is provided, which includes a conductive substrate, a first dielectric layer, and a first metal layer. The conductive substrate includes a first surface and at least one first concave located on the first surface. The first dielectric layer covers the first surface and the first concave. The first metal layer covers the first dielectric layer, wherein the first dielectric layer and the first metal layer respectively have concave structures corresponding to the first concave. A stack-type capacitor structure is also provided.