Vertical Transistor Bottom Spacer Profile Control
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Solution Overview
Problem
Conventional bottom spacer patterns in VFETs have a concave meniscus-like shape at corners where they abut source/drain junctions, leading to issues in controlling these junctions and causing device variability due to impact on deposition profiles of high-K dielectric and work-function metal layers.
Innovation Solution
A bottom spacer pattern is formed using first and second bottom spacer formations, where the first spacers have a flat profile adjacent to source/drain junctions achieved by removing a sacrificial epitaxial layer and depositing a spacer material that pinches off, filling open areas under the fins, and the second spacers have a concave meniscus-like profile, resulting in a self-aligned bottom source/drain junction with uniform effective gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bottom spacer formation is used, then the spacer pattern is formed, but the spacers have a concave meniscus-like shape at corners impacting deposition profiles and causing device variability
Solution Approach 1:
The bottom spacer formation is divided into two separate formation processes: first bottom spacers are formed with a flat profile adjacent to source/drain junctions, and second bottom spacers are formed with a concave meniscus-like profile. This segmentation allows each spacer type to serve its specific function without the detrimental effects of the unwanted profile shape on junction control.
Solution Approach 2:
Different regions of the bottom spacer structure are given different profile qualities: the first bottom spacers adjacent to source/drain junctions have a flat profile to ensure precise junction control and uniform deposition, while the second bottom spacers have a concave profile that is positioned away from the junctions where it does not impact deposition profiles or cause device variability.
2Manufacturing precision
If sacrificial epitaxial layer is removed and spacer material is deposited, then the first spacers with flat profile are formed, but additional process steps are required
Solution Approach 1:
A sacrificial epitaxial layer is grown on the bottom source/drain regions before spacer formation. This preliminary action creates a defined surface that enables subsequent selective removal and controlled spacer deposition, ensuring the first spacers achieve the desired flat profile adjacent to junctions with high precision.
Solution Approach 2:
The sacrificial epitaxial layer serves as an intermediary structure that facilitates the formation of the first bottom spacers with a flat profile. It is grown, then selectively removed to enable spacer material deposition in the exposed areas, and its controlled presence and removal are essential for achieving the pinched-off spacer geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a uniform effective gate length that is immune to process variations, improving control over bottom source/drain junctions and reducing device variability by eliminating the concave meniscus-like shape issues in the first spacers.
Implementation Method 1
removing a sacrificial epitaxial layer from on top of a bottom source/drain layer
Implementation Method 2
deposition of a first spacer material. The deposition results in the first spacer material being pinched-off
Implementation Method 3
diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.