Vertical Buried Gate Non-Volatile Memory Cell Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing UCP memory cells are limited in size reduction, which hinders the miniaturization of memory arrays, and there is a need for a more compact memory structure while maintaining efficient programming, erasing, and reading operations.
Innovation Solution
The method involves forming memory cells with a buried gate structure and using the isolation layer as a source line, allowing for a reduction in semiconductor surface area by eliminating surface transistors and using a common word line for selection transistors, enabling identical voltage application across memory cells for reading, erasing, and programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional UCP memory cell structure with surface transistors is used, then transistors can be easily manufactured and operated, but semiconductor surface area is excessively large
Solution Approach 1:
The patent applies dimensionality change by moving the selection transistor gate from the surface plane to a vertical buried structure extending into the substrate. The gate structure extends from the surface downward, creating a vertical field effect transistor where the channel is formed in the vertical dimension rather than horizontal, thereby reducing surface footprint while maintaining transistor functionality
Solution Approach 2:
The patent implements nesting by placing the selection transistor gate structure within the existing memory cell vertical stack. The buried gate is positioned between the substrate and the floating gate transistor, utilizing the vertical space already allocated for memory cell structures. This nested arrangement allows the selection transistor to share space with other cell components without increasing surface area
2Area of stationary object
If isolation layer is used as source line for selection transistors, then surface area is reduced, but voltage application control becomes more challenging
Solution Approach 1:
The patent applies universality by making the isolation layer serve multiple functions simultaneously: it acts as both the source line for the selection transistors and as the electrical isolation layer between adjacent memory cells. This multi-functional use of the isolation layer eliminates the need for separate source line structures, reducing surface area while maintaining operational control through existing isolation layer voltage control mechanisms
3Ease of manufacture
If common word line is used for selection transistors, then manufacturing is simplified, but individual cell selection control is reduced
Solution Approach 1:
The patent applies local quality by enabling different voltage conditions to be applied to different regions of the common word line. Although the word line is a single continuous structure, the buried gate configuration allows selective activation of individual cells along the word line by applying voltages to specific segments, maintaining individual cell selectability while using a common word line structure for all selection transistors
Data Source
AI summary
The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.