Solid-State Imaging Device Leakage Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional CMOS-type solid-state imaging devices with global shutter function face challenges in minimizing chip area and reducing leakage current, which affects signal quality due to differences in potential between transistors and storage capacitors.
Innovation Solution
The implementation of a solid-state imaging device with a first substrate containing photoelectric conversion units and a second substrate with signal storage circuits, where transistors are configured at different conductive type well layers, and the potential difference between the back gates of transistors is managed to minimize leakage current, using shared well regions between adjacent pixels to reduce area and enhance signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global shutter function is implemented with storage capacitor units having light-shielding properties, then simultaneous storage of signal charges is achieved, but chip area increases
Solution Approach 1:
The patent moves the signal storage function from the first substrate (photoelectric conversion substrate) to the second substrate (circuit substrate) through vertical stacking. The storage capacitor units are formed on the back surface of the second substrate, utilizing the third dimension (depth/stacking direction) to resolve the area conflict. This allows simultaneous storage of signal charges from all pixels without increasing the planar chip area.
Solution Approach 2:
The patent divides the device into two separate substrates: the first substrate for photoelectric conversion and the second substrate for signal processing and storage. By segmenting the functions across different substrates and connecting them through bonding, the patent achieves global shutter capability while maintaining compact area through vertical integration.
2Reliability
If transistors are formed at different conductive type well layers, then leakage current is reduced and signal quality is improved, but device complexity increases
Solution Approach 1:
The patent applies different conductive type well layers (first conductive type for N-type transistors, second conductive type for P-type transistors) to different regions of the second substrate. This local differentiation allows optimization of transistor characteristics in specific areas, reducing leakage current where needed while maintaining overall device functionality.
Solution Approach 2:
The patent changes the conductive type parameter of well layers to reduce leakage current. By forming N-type transistors in P-type wells and P-type transistors in N-type wells, the patent utilizes parameter changes in the semiconductor material properties to improve signal quality and reduce unwanted current leakage.
3Area of stationary object
If well regions are shared between adjacent pixels, then chip area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges adjacent well regions of the same conductive type into shared regions between multiple pixels. For example, P-type wells for N-type transistors in adjacent pixels are combined into a single shared P-type well region. This merging reduces the total number of discrete well regions, minimizing chip area while requiring precise manufacturing control.
Solution Approach 2:
The shared well regions serve multiple functions: they provide the substrate for multiple transistors from different pixels simultaneously, act as common electrical connections, and reduce overall device area. This multi-functionality allows a single well region to support multiple pixel elements, improving area efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leakage current and maintains high signal quality by optimizing the potential differences and well region sharing, thereby minimizing chip area and improving imaging performance.
Implementation Method 1
a signal charge generated and stored by a photoelectric conversion unit of a pixel on which light is incident
Data Source
AI summary
In a solid-state imaging device and an imaging device, transistors on a first substrate are configured as N-type transistors. Of transistors on a second substrate, a sampling transistor and an analog memory reset transistor connected to an analog memory are configured as P-type transistors. A difference between the potential of back gates of the sampling transistor and the analog memory reset transistor and a potential at the time of resetting the analog memory is less than a difference between the potential of a back gate of the N-type transistor and the potential at the time of resetting the analog memory.