Offset Contact Pads for Reduced Off Capacitance in Transistors
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Solution Overview
Problem
OFF-state capacitance in RF switching devices negatively affects performance by limiting speed and introducing parasitic capacitances, and existing solutions that increase source/drain spacing are impractical due to increased device area or undesirable ON-state resistance.
Innovation Solution
The use of offset contact pads on semiconductor dies, where the second set of contact pads is positioned offset with respect to the first set in a longitudinal direction, reducing OFF-state capacitance without significantly increasing device area or ON-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If source/drain spacing is increased to reduce OFF-state capacitance, then OFF-state capacitance is reduced, but device area increases
Solution Approach 1:
The patent offsets contact pads in the longitudinal direction (along the source/drain region length) rather than increasing lateral spacing. This dimensional approach reduces OFF-state capacitance by increasing the distance between overlapping contact pads while maintaining compact lateral dimensions, thus reducing device area footprint.
Solution Approach 2:
The contact pads are positioned asymmetrically with an offset along the longitudinal direction of the source and drain regions. This asymmetric positioning creates non-uniform spacing between contact pads, reducing the overlapping area and thus reducing OFF-state capacitance without requiring uniform increase in source/drain spacing.
2Object-affected harmful factors
If source/drain spacing is increased to reduce OFF-state capacitance, then OFF-state capacitance is reduced, but ON-state resistance increases
Solution Approach 1:
By offsetting contact pads longitudinally rather than increasing lateral spacing, the patent maintains optimal source/drain spacing for low ON-state resistance while reducing OFF-state capacitance through reduced contact pad overlap in the longitudinal dimension.
Solution Approach 2:
The offset configuration locally reduces capacitance at the contact pad interfaces where overlap occurs, while maintaining the overall source/drain region continuity and electrical conductivity needed for low ON-state resistance. The effect is localized to the contact regions without compromising the conductive path.
Data Source
AI summary
Systems, apparatuses and methods for reduced OFF capacitance in switching devices are disclosed. A transistor stack includes first and second doped regions serving as a source and drain, respectively of a transistor, an elongated gate structure including a first gate structure disposed between the first and second regions and serving as a gate of the transistor, a first set of electrical contact pads disposed on the first region, and a second set of electrical contact pads disposed on the second region, the second set of contact pads having an offset position with respect to the first set of contact pads in a longitudinal direction of the first and second regions.