Segmented Contact Structure for FinFET Reliability

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Solution Overview

Problem

The fabrication of finFET transistors faces challenges in producing reliable contacts that connect the source, drain, and gate, which are crucial for achieving desired performance characteristics in semiconductor integrated circuits as they scale down in size.

Innovation Solution

The method involves forming semiconductor fins on a substrate, creating a gate structure with a gate dielectric and electrode, and using epitaxial growth to form raised source/drain regions, followed by the formation of contact spacers and contacts that are electrically connected to these regions, ensuring a large contact area and improved device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional contact fabrication methods are used in finFET transistors, then the manufacturing process is simpler, but the contact quality and device performance deteriorate due to insufficient contact area

Engineering Contradiction:
Improvecontact qualityVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact structure is segmented into multiple components: a contact plug extending into the semiconductor fin, a contact collar surrounding the contact plug, and a contact pad on top. This segmentation allows each component to be optimized independently for electrical performance while managing fabrication complexity through systematic process steps.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The contact collar is formed by depositing conductive material around the contact plug, creating a nested structure where the contact collar surrounds the contact plug. This nesting increases the effective contact area and improves electrical connection without requiring separate fabrication processes for each contact component.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the contact area is increased to improve device performance, then the electrical connection quality improves, but the device dimensions increase which contradicts the scaling trend

Engineering Contradiction:
Improvedevice performanceVSAvoiddevice dimensions
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The contact structure transitions from a simple planar contact to a three-dimensional structure with vertical and radial dimensions. The contact plug extends vertically into the fin, the contact collar provides radial coverage around the plug, and this multi-dimensional approach increases contact area without increasing the lateral footprint of the device.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The contact structure concentrates electrical connection quality in specific local regions: the contact plug provides deep vertical connection into the fin, the contact collar provides lateral connection around the plug, and the contact pad provides top surface connection. This localized quality enhancement improves overall device performance without requiring uniform increases in all device dimensions.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the quality of transistor contacts, leading to improved device performance by increasing the contact area between the contacts and the epitaxy structures, thereby addressing the reliability and performance challenges in finFET transistors.

Implementation Method 1

using epitaxial growth to form raised source/drain regions

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS10269906B2Semiconductor device having two spacers
Publication Date: 2019.04.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10269906B2 patent drawing
  • US10269906B2 patent drawing
  • US10269906B2 patent drawing

AI summary

A semiconductor device includes a substrate, a source/drain feature, a gate structure, a contact, a gate spacer, and a contact spacer. The source/drain feature is at least partially disposed in the substrate. The gate structure is disposed on the substrate and adjacent to the source/drain feature. The contact is electrically connected to the source/drain feature. The gate spacer is disposed on a sidewall of the gate structure and between the gate structure and the contact. The contact spacer is disposed on the gate spacer and on a sidewall of the contact. An interface is formed between the gate spacer and the contact spacer, and a bottom surface of the contact spacer is in contact with the contact.