Wave Transistor Layout for Low On-Resistance CMOS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power MOSFETs with large gate widths face inefficiencies due to wasted layout area, increased resistance, and limitations in current capacity, as well as challenges in integrating well taps and ballast resistors, which affect their drive current and latchup characteristics.
Innovation Solution
A MOSFET design featuring a series of gates with alternating longer and shorter sections, connected by gate sections, and a straight horizontal gate, along with optimized source and drain regions and metallization layers to enhance current flow and reduce resistance, allowing for a more compact and efficient layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a waffle transistor layout with crosshatch lattice pattern is used to achieve large gate width, then the transistor can handle high current, but the poly sections where gates cross do not contribute greatly to drive current and represent wasted space
Solution Approach 1:
The gate structure is segmented into multiple fingers that are arranged in a specific pattern. Each finger is a separate conductive element that can be independently connected to source and drain regions, eliminating the wasted poly sections problem while maintaining large effective gate width for high current handling.
Solution Approach 2:
The gate fingers are arranged in a two-dimensional pattern that optimizes both the effective gate width and the contribution of each poly section to drive current. This dimensional arrangement ensures that all gate material contributes effectively to current driving while maintaining compact layout.
2Ease of operation
If metal strips are angled at 45 degrees to optimize current flow direction, then current distribution is improved, but the length of metal is increased by factor of 1.4 which increases effective Ron
Solution Approach 1:
The metallization is segmented into multiple parallel strips rather than single angled strips. This segmentation allows for optimized current distribution while reducing the effective path length and resistance by providing multiple parallel current paths.
Solution Approach 2:
Instead of using full 45-degree angled metal strips, the design uses multiple smaller metal segments that collectively provide the current distribution benefits while minimizing the total metal length and associated resistance.
3Reliability
If well taps are added to improve latchup immunity and safe operating area, then transistor reliability is improved, but the gates break sources into small isolated regions and there is no room to create butted or integrated well ties
Solution Approach 1:
The well tap connections are merged with the source region geometry itself. The source regions are designed to naturally accommodate well ties without requiring separate structures, integrating the latchup protection function into the basic device geometry.
Solution Approach 2:
The source regions serve multiple functions: they provide the primary source function for current flow, accommodate well tap connections for latchup immunity, and maintain compact layout. This multi-functionality eliminates the need for separate well tie structures.
4Reliability
If ballast resistors are added between gate and emitter to protect against ESD and balance current load, then transistor reliability is improved, but the reduced area of drain silicide requires increased drain rectangular area which grows source size
Solution Approach 1:
The ballast resistor function is merged with the drain silicide region itself. The drain silicide is designed to provide both the primary drain function and the ballast resistance for ESD protection and current balancing, eliminating the need for separate ballast resistor structures.
Solution Approach 2:
The drain silicide region serves multiple functions: primary drain current collection, ballast resistance for ESD protection, and current load balancing. This multi-functionality prevents area growth while maintaining reliability.
Data Source
AI summary
In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain regions lie between adjacent gates. Contacts are located adjacent each side of sections of the “wave” gates which connect the ends of the horizontal sections of the “wave” gates.