SRAM Back Gate Coupling via Shared Plug for ON Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in enhancing the performance of semiconductor devices, particularly SRAM memory cells, by improving the characteristics of MOSFETs and SRAM memory cells using a SOI substrate, which is difficult to apply effectively due to the complexity of integrating a double gate structure with a large number of transistors.
Innovation Solution
The semiconductor device incorporates a specific configuration of transistors and semiconductor regions in a SOI substrate, including p-type and n-type semiconductor regions isolated by an insulating layer, where the gate electrodes of access and load transistors are coupled to the back gates, allowing for improved transistor operation characteristics and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double gate structure is applied to SRAM memory cells with a large number of transistors, then transistor operation characteristics are improved and leakage current is reduced, but device complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent divides the SRAM memory cell into separate N-well and P-well regions, each containing specific transistors. The N-well contains access transistors and one load transistor, while the P-well contains the other load transistor and driver transistors. This segmentation allows independent optimization of each well region and simplifies the overall structure compared to a unified double gate approach.
Solution Approach 2:
The patent applies different well types (N-well and P-well) to different regions of the semiconductor substrate, with each well region having specific transistor configurations optimized for its function. The N-well region is optimized for access transistors while the P-well region is optimized for load and driver transistors, allowing local optimization without increasing overall device complexity.
2Productivity
If a double gate structure is applied to SRAM memory cells, then ON current is increased and threshold voltage control is improved, but manufacturing precision requirements increase
Solution Approach 1:
By segmenting the memory cell into separate N-well and P-well regions with distinct transistor assignments, the patent enables independent manufacturing processes for each well type, reducing the precision requirements compared to a monolithic double gate structure where all transistors would require identical gate configurations.
Solution Approach 2:
The patent utilizes substrate bias applied to the N-well and P-well regions to dynamically control threshold voltages of transistors. This parameter change approach allows flexible threshold voltage adjustment without requiring precise physical gate structure modifications, thereby reducing manufacturing precision requirements while maintaining high ON current capability.
3Reliability
If separate N-well and P-well regions are used to isolate transistor regions, then electrical isolation is achieved and transistor characteristics are improved, but device area increases
Solution Approach 1:
The patent merges the isolation function into the well structure itself by using deeply formed N-well and P-well regions that naturally provide electrical isolation between adjacent memory cells. The wells extend through the substrate and are connected to substrate bias, creating inherent isolation barriers without requiring additional isolation structures, thus reducing the overall memory cell area.
Solution Approach 2:
The patent achieves electrical isolation by extending the N-well and P-well regions vertically through the substrate rather than relying solely on lateral isolation structures. This dimensional transition from two-dimensional planar isolation to three-dimensional vertical isolation allows for more compact memory cell layouts while maintaining effective electrical separation between adjacent cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the operating characteristics of transistors, increases ON current, and allows for individual control of threshold voltage, thereby improving the overall performance and efficiency of SRAM memory cells.
Implementation Method 1
an insulating layer disposed under the first active region and the second active region
Implementation Method 2
the gate electrodes of access and load transistors are coupled to the back gates, allowing for improved transistor operation characteristics
Data Source
AI summary
Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.