FEOL MIM Capacitor Structure Reducing Resistance Load
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Solution Overview
Problem
Existing metal-insulator-metal (MIM) capacitors and deep trench capacitors require multiple lithographic masks and processes, leading to high resistance loads due to their physical distance from metal-oxide semiconductor field effect transistors (MOSFET) circuits and complex wiring levels.
Innovation Solution
A front-end-of-line MIM capacitor structure is developed, featuring a semiconductor substrate with a dielectric-filled trench isolation, a polysilicon capacitor plate with a surrounding spacer, a silicide layer, a capacitor dielectric layer, and a contact in the interlayer dielectric, allowing for direct contact with a metal layer and reducing the number of masks required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BEOL MIM capacitors or FEOL deep trench capacitors are used, then capacitor functionality is achieved, but the physical distance from MOSFET circuits creates high resistance load
Solution Approach 1:
The capacitor structure is merged with the transistor fabrication process by forming the first capacitor plate simultaneously with the transistor gate structure during FEOL processing. This integration places the capacitor in close proximity to the MOSFET circuit, eliminating the need for separate BEOL capacitor structures and reducing resistance load from multiple wiring levels.
2Manufacturing precision
If multiple lithographic masks and processes are used for capacitor formation, then precise capacitor structure is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The capacitor formation process is merged with the transistor fabrication sequence. The first capacitor plate is formed using the same polysilicon deposition and patterning steps as the transistor gate, eliminating the need for separate lithographic masks and processes for capacitor creation.
Solution Approach 2:
The capacitor plate is formed preliminarily during the FEOL process before backend metallization layers are deposited. This preliminary formation allows the capacitor structure to be established using existing process steps without requiring additional masking and patterning operations.
3Loss of time
If FEOL deep trench capacitors are used, then early formation is achieved, but physical distance from MOSFET circuits creates high resistance load
Solution Approach 1:
The capacitor is merged into the FEOL process timeline, forming the first capacitor plate simultaneously with the transistor gate structure. This timing ensures early formation while maintaining close proximity to the MOSFET circuit, avoiding the high resistance load issue associated with physically distant capacitor placements.
Data Source
AI summary
A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.