Antifuse Oxide Layer Thickness for Predictable Breakdown
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Solution Overview
Problem
Existing antifuse designs face challenges in scalability to advanced technology nodes below 90 nm, where the thin gate dielectric layer makes breakdown behavior unpredictable and leakage currents similar before and after programming, making it difficult to sense programming.
Innovation Solution
The use of a thicker oxide film, such as the resist protective oxide (RPO) layer, as the capacitor dielectric in a separate process step from the gate dielectric, which is formed during the CMOS process and used only for the antifuse, allowing for predictable programming behavior across different technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate dielectric layer is used as the capacitor dielectric layer in standard CMOS process, then the fabrication process is simplified and can be done during standard CMOS process, but the breakdown behavior becomes unpredictable at advanced technology nodes below 90 nm and leakage current becomes similar before and after programming
Solution Approach 1:
The patent segments the gate dielectric layer and capacitor dielectric layer into separate layers. The gate dielectric layer is formed during standard CMOS process, while a separate thicker oxide layer is formed specifically for the capacitor dielectric. This segmentation allows each layer to be optimized independently, maintaining ease of manufacture while ensuring reliable breakdown behavior at advanced technology nodes.
Solution Approach 2:
The patent applies local quality by making the capacitor dielectric layer (oxide layer) substantially thicker than the gate dielectric layer. This localized thickness variation in the oxide layer provides predictable breakdown behavior and distinguishable leakage current characteristics specifically at the capacitor region, while the gate dielectric maintains its standard thickness for CMOS operation.
2Device complexity
If the gate dielectric layer is used as the capacitor dielectric layer, then no additional layers need to be added to CMOS process, but it becomes difficult to sense programming due to similar leakage currents before and after programming
Solution Approach 1:
The patent changes the thickness parameter of the oxide layer used as capacitor dielectric. By making the oxide layer substantially thicker than the gate dielectric layer, the capacitor exhibits distinct electrical characteristics including lower leakage current before programming and clearly distinguishable breakdown behavior, enabling easy programming detection without adding significant device complexity.
3Reliability
If a thicker oxide layer is used as capacitor dielectric in a separate process step, then predictable programming behavior and distinguishable breakdown are achieved, but the fabrication process becomes more complex
Solution Approach 1:
The patent performs the oxide layer formation as a preliminary action before standard CMOS processing. By forming the thicker oxide layer on the substrate first, and then proceeding with standard CMOS steps (gate dielectric formation, transistor fabrication), the patent integrates the antifuse structure into the existing CMOS process flow without requiring significant process reorganization or adding layers during critical CMOS steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains low leakage current and clearly distinguishable breakdown and programming behaviors, ensuring reliable antifuse operation even at smaller technology nodes without adding layers to the CMOS process.
Implementation Method 1
The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse
Data Source
AI summary
A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.