Semiconductor Device With Fin-Shaped Pillar And Magnetic Tunnel Junction
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Solution Overview
Problem
Current semiconductor device structures, such as STT-MRAM arrays and surrounding gate transistors, face challenges in reducing cell area and efficiently forming source lines due to the difficulty in introducing impurities into thin silicon pillars and the increased size of bit cells.
Innovation Solution
The semiconductor device employs fin-shaped and pillar-shaped semiconductor layers with specific gate and contact electrode configurations, including insulating films and diffusion layers, to form magnetic tunnel junction memory elements, allowing for reduced cell area and parallel source and bit lines, and utilizing metal gate lines for high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If surrounding gate transistors with pillar-shaped silicon are used, then the gate can surround the channel, but it becomes increasingly difficult to introduce impurity into the silicon pillar as it becomes thinner
Solution Approach 1:
The patent changes the material parameter from silicon to silicon-germanium alloy, which has different physical properties that facilitate impurity introduction. By adjusting the composition ratio of Si and Ge, the patent optimizes the balance between maintaining the pillar structure and enabling effective impurity doping, thus resolving the manufacturing difficulty while preserving the surrounding gate configuration.
Solution Approach 2:
The patent employs composite materials by creating a pillar-shaped semiconductor layer from silicon-germanium alloy instead of pure silicon. This composite structure combines the advantages of both materials: silicon provides the necessary semiconductor properties while germanium enhances the ability to introduce impurities, thereby solving the contradiction between structural complexity and manufacturing ease.
2Ease of manufacture
If planar transistors are used with source lines extending perpendicular to word lines, then the structure can be formed, but an additional metal layer is needed and the bit cell area is increased
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a three-dimensional surrounding gate structure where the gate wraps around the pillar-shaped channel. This dimensional change allows source lines to be formed at different levels (z-dimension) rather than requiring additional metal layers in the same plane, thereby reducing the bit cell area while maintaining manufacturability.
Solution Approach 2:
The surrounding gate structure embodies the nesting principle by having the gate electrode wrap around and enclose the pillar-shaped semiconductor layer, which itself is positioned within the fin structure. This nested configuration enables compact integration of multiple functions within the same footprint, reducing the overall bit cell area without compromising ease of manufacture.
3Ease of operation
If the threshold voltage of SGT is determined by decreasing impurity concentration of channel, then the threshold voltage can be controlled, but the impurity introduction becomes increasingly difficult as the silicon pillar becomes thinner
Solution Approach 1:
The patent changes the material composition parameter from pure silicon to silicon-germanium alloy, which fundamentally alters the impurity introduction characteristics. This parameter change enables effective doping even in thin pillar structures, allowing threshold voltage control to be achieved without the manufacturing difficulties that plague thin silicon pillars.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively decreases the cell area, allows source lines to be formed at a different level than bit lines, and enables high-speed operation while avoiding misalignment issues, ensuring proper insulation and functionality.
Implementation Method 1
a first magnetic tunnel junction memory element disposed on the second contact electrode
Implementation Method 2
a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer
Implementation Method 3
a first gate insulating film disposed around the first pillar-shaped semiconductor layer
Data Source
AI summary
A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode.