Tile-Based Place-and-Route for HBM PHY Interconnects
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Solution Overview
Problem
Current automatic routing tools face challenges in generating efficient routing solutions for High Bandwidth Memory (HBM)-based IC devices due to the large number of densely-packed contact pads and complex signal line connections, leading to increased production time and resource consumption.
Innovation Solution
A flexible tile-based place-and-route methodology using pre-generated physical layer (PHY) tiles that simplify the routing process by providing pre-routed conductive paths from densely-packed contact pads to orthogonal edges, allowing existing routing tools to quickly generate parallel signal lines between mirrored pin sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional automatic routing tools are used to route signal lines between densely-packed contact pads, then routing completeness can be achieved, but processing time and computational resources increase significantly
Solution Approach 1:
The routing process is segmented into two distinct phases: (1) generating a simplified routing graph that identifies feasible routing regions and valid transitions between contact pads, and (2) selecting optimal routing paths based on design criteria. This segmentation reduces the computational complexity by separating the complex geometric routing problem from the path selection problem, enabling faster processing while maintaining routing completeness.
Solution Approach 2:
The method performs preliminary actions by pre-identifying feasible routing regions and valid transitions between contact pads before actual path selection. The routing graph is constructed in advance with all possible routing options and constraints already encoded, allowing the subsequent path selection to proceed efficiently without re-evaluating geometric constraints during the routing decision process.
2Manufacturing precision
If manual routing methods are used for HBM contact pad interconnection, then routing quality can be maintained, but production efficiency decreases
Solution Approach 1:
The system performs self-service by automatically generating routing graphs and selecting optimal paths without requiring manual intervention. The automated method encodes design rules, geometric constraints, and routing criteria into the routing graph construction and path selection algorithms, enabling the system to produce high-quality routing solutions independently while maintaining productivity.
3Manufacturing precision
If detailed routing paths are calculated for all contact pad pairs, then routing optimality can be achieved, but computational complexity increases
Solution Approach 1:
The routing problem is segmented into graph construction and path selection phases, where the graph encapsulates all geometric and constraint information. This segmentation reduces computational complexity by pre-processing the complex geometric relationships into a simplified graph structure that can be queried efficiently during path selection without re-calculating geometric constraints.
Solution Approach 2:
The routing graph serves as an intermediary data structure that mediates between the complex geometric routing problem and the simpler path selection problem. It transforms detailed geometric constraints into discrete graph edges and nodes, allowing optimal paths to be selected through graph algorithms without directly manipulating complex geometric calculations.
Data Source
AI summary
A flexible tile-based place-and-route methodology utilizes pre-generated physical layer (PHY) tiles to greatly simplify the task of automatically generating routing solutions between associated PHYs disposed on a memory device and a corresponding processor for any selected floorplan positioning of the memory device relative to the corresponding processor. The PHY tiles are pre-generated software-based layout descriptions that model the densely-packed 2D contact PHY pad arrays, and also comprise partial layout features including signal line segments that escape routing pins from the 2D contact pads to an orthogonal (straight-line) edge of the PHY tile and disposed in design-rule-compliant spaced-apart arrangements. Optional 45-degree jog line segments are utilized to efficiently correct for alignment offsets between the memory PHY and processor PHY.