Gate-to-Source/Drain Contact Formation in Vertical Transistors
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Solution Overview
Problem
In the fabrication of semiconductor devices, particularly in forming gate structure-to-source/drain conductive contacts on vertical transistor devices, existing methods face challenges in achieving reliable and efficient cross-coupling, which affects the performance and durability of memory devices like SRAM cells.
Innovation Solution
A novel method involving etching processes to form gate-to-source/drain contact openings, depositing a continuous conductive gate electrode material, and selectively recessing it to create separate gate structures for conductive coupling between vertical transistors, enabling effective conductive contact formation between gate structures and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used, then manufacturing simplicity is maintained, but conductive coupling reliability between gate structure and source/drain regions deteriorates
Solution Approach 1:
The patent segments the continuous gate electrode material into separate gate structures through selective etching, creating distinct conductive regions that can be independently coupled to source/drain regions. This segmentation enables reliable conductive coupling by establishing defined contact pathways between the gate structure and source/drain regions, resolving the reliability issue while managing complexity through systematic process steps.
Solution Approach 2:
The patent applies preliminary action by first forming the continuous gate electrode material layer before selective etching to create the final gate structures. This preliminary formation ensures complete coverage and consistent material properties, and the subsequent selective etching process then creates the necessary conductive couplings, thereby improving reliability while maintaining manageable process complexity.
2Productivity
If gate structure-to-source/drain conductive contact is formed, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating specific conductive contact regions through selective etching of the continuous gate electrode material. The etching process targets particular locations where gate-to-source/drain coupling is needed, while leaving other regions intact. This localized modification achieves the necessary conductive pathways with controlled precision, improving device performance while managing manufacturing precision requirements through targeted process steps.
3Reliability
If etching processes are used to form contact openings, then conductive coupling is achieved, but process time increases
Solution Approach 1:
The patent merges multiple functions into the selective etching process: it removes spacer material to form contact openings and simultaneously creates the final gate structure geometry from the continuous gate electrode material. This combined approach achieves conductive coupling while reducing the number of separate process steps, thereby managing fabrication time while maintaining reliable contact formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the stability and performance of memory devices by ensuring robust conductive coupling, thereby improving the reliability and durability of semiconductor devices, particularly in SRAM cells, by allowing for precise control over the potential margins of charge storage nodes.
Implementation Method 1
performing at least one first etching process to remove a portion of at least a layer of a bottom spacer material positioned above the first bottom source/drain (S/D) region so as to thereby form a gate-to-source/drain contact opening that exposes a portion of the first bottom S/D region
Implementation Method 2
forming a continuous conductive gate electrode material layer above the first and second bottom S/D regions and within the gate-to-source/drain contact opening
Implementation Method 3
performing at least one second etching process to remove a portion of the continuous gate electrode material layer so as to form first and second separate gate structures for the first and second vertical transistors, respectively
Data Source
AI summary
In one example, the method includes removing a portion of at least a layer of a bottom spacer material positioned above a first bottom source/drain (S/D) region of a first vertical transistor so as to thereby form a gate-to-source/drain contact opening that exposes a portion of the first bottom S/D region, forming a continuous conductive gate electrode material layer above the first bottom S/D region and a second bottom S/D region and within the gate-to-source/drain contact opening, and removing a portion of the continuous gate electrode material layer so as to form first and second separate gate structures for the first and second vertical transistors, respectively, wherein a portion of the second gate structure is positioned within the gate-to-source/drain contact opening, thereby conductively coupling the second gate structure to the first bottom S/D region.