Semiconductor Integrated Circuit ESD Protection via Diffusion Resistance
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in achieving sufficient ESD resistance in Tie-High, Tie-Low cells, and decoupling cells due to reduced leakage current, which makes it difficult to stabilize the potential of floating common gates, especially when power is frequently turned on or off, leading to inadequate resistance.
Innovation Solution
The semiconductor integrated circuit configuration includes a common gate connected to a low-voltage or high-voltage power line through a diffusion area acting as a resistance element, which stabilizes the potential of the common gate independently of transistor threshold voltages, thereby enhancing ESD resistance without requiring external resistance components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If leakage current is reduced to lower power consumption, then power consumption decreases, but ESD resistance deteriorates because the common gate potential cannot be stabilized
Solution Approach 1:
A resistance element is introduced as an intermediary component between the common gate and the power line. This resistance element enables controlled charge/discharge of the common gate potential, stabilizing it during ESD events even when transistor leakage current is minimized for low power consumption.
Solution Approach 2:
The invention changes the electrical parameters of the common gate node by adding a dedicated resistance element that controls the time constant for charge/discharge. This allows the common gate potential to be stabilized at appropriate levels during ESD events, resolving the conflict between low leakage current operation and ESD protection.
2Reliability
If external resistance components are added to stabilize common gate potential, then ESD resistance improves, but device complexity increases
Solution Approach 1:
The resistance element is merged with the existing transistor structure by forming it within the same semiconductor substrate using the same fabrication processes. This integration approach adds ESD protection functionality without requiring separate external resistance components, thereby maintaining device simplicity.
Solution Approach 2:
The resistance element serves multiple functions: it stabilizes the common gate potential during ESD events, controls charge/discharge timing, and is fabricated using the same process steps as the transistors. This multi-functionality reduces the need for additional dedicated components for ESD protection.
3Device complexity
If resistance element is integrated within transistor structure, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The impurity regions that form the resistance element are created during the preliminary transistor fabrication steps, specifically during the well formation and doping processes. By preparing the resistance structure in advance as part of the standard transistor manufacturing sequence, additional precision-critical steps are avoided.
Solution Approach 2:
The invention utilizes standard doping concentration ranges and impurity region dimensions that are already established in the transistor fabrication process. By selecting doping parameters that fall within existing process control capabilities, the need for ultra-precise manufacturing is minimized while achieving the required resistance values for ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves ESD resistance by shortening charge/discharge times and stabilizing the common gate potential, allowing for effective operation of Tie-High, Tie-Low cells, and decoupling cells without increasing circuit area, as the diffusion area functions as an integrated resistance element.
Implementation Method 1
a resistance element, one end of which is connected to the gates, and the other end of which is connected to one end of the second transistor, wherein the resistance element includes a diffusion area corresponding to a source or a drain of the second transistor
Data Source
AI summary
A semiconductor integrated circuit comprises first and second transistors, and a resistive element. The first transistor includes first and second regions of first conductivity type in a first well region of opposite conductivity type, and a first gate electrode on the first well region between the first and second regions. The second transistor includes third and fourth region of second conductivity type in a second well region of opposite conductivity type, and a second gate electrode on the second well region between the third and fourth regions. The first region is connected to a first line, and the third and fourth regions are connected to a second line. The resistance element includes a first end connected to the first and second gate electrodes, a second end connected to the second line, and a resistive electrical path between the first and second ends including a portion of the third region.