Dummy Deep Trenches Stabilize eDRAM Etch Uniformity

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Solution Overview

Problem

The structural features and performance of deep trench capacitors in semiconductor chips are dependent on the local device environment, leading to variations in trench profiles and depths, which affects the areal density and device leakage.

Innovation Solution

Forming dummy deep trenches in logic device regions and deep trench capacitors in memory device regions, with conductive material portions recessed to avoid electrical contact with semiconductor fins, and using dielectric material to encapsulate the conductive portions, thereby isolating them from the logic device region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If deep trench capacitors are formed in memory device regions only, then the manufacturing process is simpler, but the trench etch process becomes unstable and trench profiles vary due to pattern factor dependency

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidtrench profile uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent creates dummy deep trenches in logic device regions that copy the structure and etch conditions of functional deep trench capacitors. These dummy trenches are non-functional (filled with dielectric material and electrically isolated) but serve to replicate the etch process conditions, thereby stabilizing the trench etch process across the entire substrate and ensuring uniform trench profiles in both memory and logic regions.

Inventive Principle:
Principle #26Copying

2Manufacturing precision

If dummy deep trenches are formed in logic device regions, then trench etch process stability improves, but device complexity increases due to additional structures

Engineering Contradiction:
Improvetrench etch process stabilityVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts the essential function of dummy trenches (etch process stabilization) from the functional requirements of deep trench capacitors. By creating non-functional dummy trenches filled with dielectric material and electrically isolating them from logic device fins, the patent removes the harmful electrical interaction while retaining the beneficial etch process stabilization effect.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If conductive material portions contact semiconductor fins in logic device region, then electrical functionality is achieved, but device leakage increases

Engineering Contradiction:
Improveelectrical functionalityVSAvoiddevice leakage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces dielectric material as an intermediary between the conductive material portions in dummy trenches and the semiconductor fins in logic device regions. This dielectric layer completely encapsulates the conductive material, preventing any electrical contact while maintaining the structural presence needed for etch process stabilization.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9343320B2Pattern factor dependency alleviation for eDRAM and logic devices with disposable fill to ease deep trench integration with fins
Publication Date: 2016.05.17 GLOBALFOUNDRIES US INC
  • US9343320B2 patent drawing
  • US9343320B2 patent drawing
  • US9343320B2 patent drawing

AI summary

Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory device region. Semiconductor fins are formed over a top surface prior to forming trenches, and disposable material is filled around said semiconductor fins. A top surface of said disposable filler material layer can be coplanar with a top surface of said semiconductor fins, which eases deep trench formation. Conductive material portions of the dummy deep trenches can be recessed to avoid electrical contact with semiconductor fins within the logic device region, while an inner electrode of each deep trench can contact a semiconductor fin within the memory device region. A dielectric material portion can be formed above each conductive material portion of a dummy deep trench.