Semiconductor Dummy Gate Oxidation for CMP Protection
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Solution Overview
Problem
The existing semiconductor fabrication methods for PMOS transistors face issues with over-polishing during the chemical mechanical polishing (CMP) process, leading to severe over-polishing of silicon oxide layers and dummy gates, which results in short circuits between adjacent metal gates due to residual metal layers on the silicon oxide layer, causing performance failures.
Innovation Solution
A method is introduced where a protective layer is formed on the second dummy gate by oxidizing its top portion to prevent over-polishing, and a dielectric layer is formed to level with the dummy gates, ensuring that the CMP process does not excessively polish the silicon oxide layer, thereby preventing the formation of polishing dishes and residual metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to remove metal layers, then metal gates are formed, but over-polishing occurs on silicon oxide layer and dummy gates causing short circuits
Solution Approach 1:
A protective layer is formed on the dummy gate before the CMP process. This preliminary protective structure prevents the dummy gate and underlying silicon oxide layer from being over-polished during subsequent CMP processing, thereby avoiding short circuits between adjacent metal gates while still allowing precise metal gate formation.
2Ease of manufacture
If CMP process is performed to form metal gates, then gate structures are created, but residual metal layers remain on silicon oxide layer causing short circuits
Solution Approach 1:
The protective layer acts as an intermediary between the dummy gate/silicon oxide layer and the CMP process. It allows the CMP process to proceed easily for metal gate formation while preventing metal residues from contaminating the silicon oxide layer, thus eliminating short circuit issues.
3Measurement precision
If dummy gates are used for process alignment, then fabrication accuracy is improved, but they are damaged by over-polishing during CMP
Solution Approach 1:
The protective layer is formed on the dummy gate before the CMP process, preserving the dummy gate's structural integrity during metal gate formation. This allows the dummy gate to continue serving as an alignment reference without being damaged by over-polishing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents over-polishing and short circuits, enhancing the performance and reliability of PMOS transistors by maintaining the integrity of the dielectric layer and preventing metal residue formation, thus ensuring the desired performance of semiconductor devices.
Implementation Method 1
oxidizing a top portion of the second dummy gate to form a protective layer to prevent over-polishing on the second region on the second dummy gate
Data Source
AI summary
A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region; and forming at least one first dummy gate in the first region and at least one second dummy gate in the second region. Further, the method includes forming a dielectric layer with a top surface leveling with a surface of the first dummy gate on the semiconductor substrate; oxidizing a top portion of the second dummy gate to form a protective layer to prevent over-polishing on the second region; removing the first dummy gate to form a first gate trench; forming a first metal layer to fill the first gate trench and cover the protective layer and the dielectric layer; and removing a portion of the first metal layer higher than the dielectric layer to form a first metal gate in the first gate trench.