FinFET Fabrication Uniformity via Segmented Isolation Trenches
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Solution Overview
Problem
Fabrication of FinFET integrated circuits on bulk semiconductor substrates faces challenges with thickness uniformity and isolation between fins and active areas, leading to non-planar surfaces and variations in fin height and channel width due to the combination of shallow and deep insulator-filled trenches.
Innovation Solution
The method involves etching a semiconductor substrate to form a uniform array of fins across chip areas, depositing and planarizing an oxide layer, and using an isolation hard mask to etch trenches and fill them with insulating material, ensuring uniform isolation and fin height across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow and deep insulator-filled trenches are used for isolation between fins and active areas, then isolation is achieved, but non-planar surfaces and variation in fin height occur due to dishing during etch or planarization
Solution Approach 1:
The isolation structure is segmented into two distinct components: shallow trenches filled with first insulator material for fin isolation, and deep trenches filled with second insulator material for active area isolation. This segmentation allows each trench type to be optimized independently, preventing the dishing problems that occur when attempting to planarize over mixed-density regions.
Solution Approach 2:
Different insulator materials are used in different locations: a first insulator material (such as silicon nitride) is deposited in shallow trenches between fins, while a second insulator material (such as silicon dioxide) is deposited in deep trenches between active areas. This local differentiation in material properties prevents uniform planarization issues across the entire substrate.
2Ease of manufacture
If SOI substrates are used for FinFET fabrication, then fin isolation is easily achieved by etching away semiconductor material, but substrate cost increases and crystalline quality decreases
Solution Approach 1:
Insulator materials are introduced as intermediary substances to achieve fin isolation on bulk semiconductor substrates. Instead of relying on the semiconductor-on-insulator structure of SOI substrates, the patent uses deposited insulator layers (silicon nitride, silicon dioxide) in trenches to provide the necessary isolation, thereby maintaining the advantages of bulk substrates while achieving SOI-like isolation characteristics.
3Productivity
If transistor size is decreased to increase transistor density, then more transistors can be placed on the substrate, but transistor performance deteriorates
Solution Approach 1:
The patent transitions from planar transistor geometry to three-dimensional FinFET structures where the channel extends vertically along the sidewalls of fins. This dimensional change allows the channel width to increase in the vertical direction without increasing the lateral footprint, thereby maintaining high transistor density while improving transistor performance through increased effective channel width and enhanced gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves uniform fin height and channel width, addressing the issues of non-planarity and variability in FinFET characteristics by maintaining consistent fin height and channel width across the substrate, thereby enhancing the uniformity and performance of FinFET integrated circuits.
Implementation Method 1
The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips
Implementation Method 2
An oxide is deposited to fill between the fins
Implementation Method 3
is etched to recess the top of the oxide below the top of the fins
Implementation Method 4
is used as an etch mask to etch trenches in the substrate defining a plurality of active areas
Implementation Method 5
The trenches are filled with an insulating material to isolate between adjacent active areas
Data Source
AI summary
Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas.