Non-volatile Floating Gate Memory Cells with Sharp Polysilicon Edges
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Solution Overview
Problem
Conventional non-volatile memory floating gate transistors face challenges in efficiently programming and erasing due to limitations in tunneling efficiency and reliability, particularly under high gate voltages, which affect the thickness and performance of tunnel dielectric layers.
Innovation Solution
The fabrication of storage transistors with controlled sharp polycrystalline silicon edges enhances tunneling between layers, allowing for improved inter-poly tunneling during both program and erase operations, using first and second polysilicon layers with a tunneling dielectric layer in between, and enabling enhanced Fowler-Nordheim tunneling for electron injection and removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating gate transistors are used with standard tunnel dielectric layers, then the basic memory function is achieved, but tunneling efficiency is insufficient and reliability is reduced
Solution Approach 1:
The patent applies local quality by creating sharp polysilicon edges at specific locations (interfaces between floating gate and control gate, and between floating gate and substrate) rather than modifying the entire structure. These localized sharp edges concentrate electric fields precisely where needed to enhance Fowler-Nordheim tunneling efficiency during programming and erasing operations, directly improving tunneling efficiency without compromising overall device reliability
Solution Approach 2:
The patent changes the geometric parameter of the polysilicon layers by forming sharp edges with specific angle ranges (30-60 degrees). This parameter change in the edge geometry modifies the electric field distribution and enhances tunneling characteristics, resolving the contradiction between tunneling efficiency and reliability by optimizing the field concentration at critical interfaces
2Ease of manufacture
If memory cell size is reduced to lower production costs, then manufacturing cost decreases, but tunneling efficiency and reliability may be compromised
Solution Approach 1:
By concentrating the tunneling enhancement mechanism at specific sharp edges rather than requiring uniform enhancement across the entire memory cell structure, the patent enables smaller memory cell designs. The localized sharp edges provide sufficient tunneling efficiency even in reduced-size cells, allowing cost reduction through miniaturization while maintaining reliability
Solution Approach 2:
The patent introduces asymmetry in the polysilicon layer geometry by creating sharp edges with specific angle characteristics at critical interfaces. This asymmetric geometry optimizes electric field concentration in a space-efficient manner, enabling reliable tunneling in compact memory cell designs that reduce production costs
3Speed
If thinner tunnel dielectric layers are used to improve tunneling efficiency, then programming and erasing speed increases, but device reliability decreases
Solution Approach 1:
The patent changes the geometric parameter of the polysilicon layers by forming sharp edges with specific angle ranges (30-60 degrees). This parameter change in the edge geometry modifies the electric field distribution and enhances tunneling characteristics, resolving the contradiction between tunneling efficiency and reliability by optimizing the field concentration at critical interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces memory cell size, lowers production costs, and allows for thicker tunneling dielectric layers, thereby enhancing the reliability and efficiency of non-volatile memory operations.
Implementation Method 1
The storage transistor can use enhanced Fowler-Nordheim tunneling for both removing electrons from and injecting electrons into the floating gate
Implementation Method 2
Under high gate voltages, electrons can tunnel through tunnel dielectric layers, e.g., silicon dioxide, to move into or out of the floating gate
Data Source
AI summary
A storage transistor for non-volatile memory can be fabricated to create controlled sharp polycrystalline silicon (polysilicon) edges. The edges concentrate the electric field in the storage transistor and are used to enhance tunneling between layers of polysilicon for both program and erase operations. The storage transistor includes first and second polysilicon layers and a tunneling dielectric layer between the first and second polysilicon layers, and the second polysilicon layer includes at least a first edge extending towards the first polysilicon layer.