Metal-Filled Inter-Fin Gaps in Non-Planar Transistors
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Solution Overview
Problem
Nonplanar multigate semiconductor devices like FinFETs face issues with keyhole and void formation in the silicon gate layer, which affect performance and yield, and existing stress enhancement methods are suboptimal for these devices.
Innovation Solution
A non-planar semiconductor transistor device with a gate stack comprising a dielectric layer, a work-function electrode layer, and a metal layer that fills the gap between conductive channels, where the metal layer is stress-engineered to apply compressive or tensile stress and is formed using techniques like sputtering or chemical vapor deposition, reducing voids and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a silicon containing layer is deposited in the gate between conducting channels to form FinFETs, then the gate structure is formed, but key holes and voids form within the layer reducing performance and yield
Solution Approach 1:
The patent changes the material parameter from silicon-containing dielectric to metal fill material, fundamentally altering the deposition process and eliminating void formation. The metal layer is deposited using sputtering or electroplating techniques that ensure complete gap filling without the keyhole effects experienced with silicon deposition
Solution Approach 2:
The gate structure becomes a composite system combining the dielectric layer, work function metal layer, and stress-engineered metal fill layer. This composite approach allows each material to perform its specific function: the dielectric provides electrical isolation, the work function layer sets the gate potential, and the metal fill provides stress control while eliminating voids
2Stress or pressure
If existing stress enhancement methods are applied to planar CMOS devices, then some stress is introduced, but the stress enhancement is suboptimal for nonplanar multigate transistors
Solution Approach 1:
The patent applies local quality by engineering the metal layer to provide different stress states (tensile or compressive) tailored to specific device locations and types. The stress characteristics are optimized locally for each FinFET configuration rather than applying a uniform stress enhancement approach across the entire device
Solution Approach 2:
The patent changes the stress application mechanism by using a metal layer with controlled intrinsic stress properties deposited conformally over the gate structure. This allows precise control of stress magnitude and direction through material selection and deposition parameters, achieving optimal stress enhancement for nonplanar multigate transistors
3Manufacturing precision
If the metal layer is deposited to fill gaps between conductive channels, then voids are reduced, but the deposition process complexity increases
Solution Approach 1:
The gate structure is segmented into distinct functional layers: dielectric layer, work function metal layer, and stress metal fill layer. This segmentation allows each layer to be optimized independently for its specific function while simplifying the overall manufacturing process through standardized deposition sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces voids in the inter-fin region, enhances stress distribution, and improves the performance of nFET and pFET-type FinFETs by filling gaps and applying targeted stress, leading to high-density, high-performance transistors.
Implementation Method 1
The metal layer may be formed over the work-function layer by sputtering, physical vapor deposition, atomic layer deposition or chemical vapor deposition.
Implementation Method 2
The metal layer may be formed over the work-function layer by sputtering, physical vapor deposition, atomic layer deposition or chemical vapor deposition.
Implementation Method 3
The metal layer may be formed to have an intrinsic state of compressive or tensile stress.
Data Source
AI summary
A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.