Array Substrate Parallel Common Electrode Resistance Reduction
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Solution Overview
Problem
Liquid crystal displays face issues such as becoming greenish and exhibiting non-uniform gray scale due to increased leakage current caused by misalignment or manufacturing failures, leading to display defectiveness like X-talk, especially in high-resolution products, where the resistance of the common electrode is a concern.
Innovation Solution
The array substrate design includes a first and second gate metal layer with a second common electrode line connected in parallel to the first common electrode line, and a resin layer with electrodes configured to generate an electric field, ensuring the semiconductor layer is protected from light irradiation and maintaining transmittance, thereby reducing the resistance of the common electrode without affecting the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the line width of common electrode is increased to reduce resistance, then the resistance of common electrode is reduced, but the aperture ratio becomes smaller
Solution Approach 1:
The patent divides the common electrode into multiple segments (first common electrode line and second common electrode line) that are disposed in different layers. This segmentation allows the electrode structure to achieve lower resistance through multiple pathways without requiring an increase in the line width of individual electrodes, thereby maintaining the aperture ratio.
Solution Approach 2:
The patent transitions from a single-layer common electrode structure to a multi-layer structure by disposing the first common electrode line in one layer and the second common electrode line in another layer. This dimensional change enables resistance reduction through vertical stacking and parallel pathways without consuming additional horizontal space that would reduce the aperture ratio.
2Reliability
If the semiconductor layer is exposed due to misalignment or manufacturing failures, then exterior light irradiates the semiconductor layer causing increased leakage current, but adding protective structures may block light and reduce transmittance
Solution Approach 1:
The patent merges the protective function with the existing gate metal layers. The first gate metal layer and second gate metal layer serve dual purposes: they function as gate electrodes for the thin film transistor and simultaneously act as protective shields against exterior light irradiation. This merging eliminates the need for additional protective structures that would block light and reduce transmittance.
Solution Approach 2:
The gate metal layers are designed to perform multiple functions: electrical gating control and optical shielding. By making the gate metal layers serve both purposes, the patent prevents light-induced leakage current without introducing separate protective elements that would compromise display transmittance and picture quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution mitigates display defectiveness like greenish tint and X-talk while maintaining transmittance, enhancing the picture quality of liquid crystal displays, particularly for high-resolution products by reducing common electrode resistance without compromising aperture ratio.
Implementation Method 1
the first gate metal layer and the second gate metal layer are used to block exterior light, so that the semiconductor layer is not irradiated by the exterior light
Implementation Method 2
a first electrode and a second electrode configured to generate an electric field therebetween to drive liquid crystals
Data Source
AI summary
A array substrate is disclosed. The array substrate includes: a substrate (10); and a first gate metal layer (111), a first gate insulating layer (121), a semiconductor layer (13) and a source-drain electrode layer (14) disposed in this order on the substrate from bottom to top. The array substrate (10) further includes a second gate insulating layer (122) disposed on the source-drain electrode layer (14); and a second gate metal layer (112) disposed on the second gate insulating layer (122). A method of manufacturing an array substrate is also disclosed.


