Low Voltage Selftime Tracking Circuitry for Write Assist
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Solution Overview
Problem
Conventional write replica paths in SRAM arrays are inoperable at low voltage applications below the desired operating voltage, leading to inconsistent and varying write duration tracking, which affects SRAM performance.
Innovation Solution
The design includes a SRAM cell with specific transistor configurations and pass gate arrangements that allow parallel operation of pass gates to effectively pull down signals against the pull-up provided by PMOS transistors, ensuring successful write operations even at low supply voltages, by coupling pass gates in parallel and using a floating node to enhance the write replica path functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write replica paths are used in low voltage applications, then the SRAM array cannot operate, but the write duration tracking becomes inconsistent and varying
Solution Approach 1:
The patent applies local quality by creating a specialized low-voltage write replica path with distinct circuit characteristics. The low-voltage path uses different transistor sizing and pass gate configurations specifically optimized for low-voltage operation, while the high-voltage path maintains conventional design. This localized optimization allows the write replica path to function reliably at low voltages without affecting the main SRAM array operation.
Solution Approach 2:
The patent segments the write replica path into separate low-voltage and high-voltage paths. The low-voltage write replica path is isolated from the high-voltage path, allowing independent optimization and operation. This segmentation enables the system to maintain consistent write duration tracking at low voltages through the dedicated low-voltage path while the high-voltage path remains available for normal operation.
2Reliability
If pass gates are coupled in parallel to pull down signals against PMOS pull-up, then write operations succeed at low voltages, but the circuit complexity increases
Solution Approach 1:
The patent merges multiple pass gates in parallel configuration within the low-voltage write replica path to enhance the pull-down capability. By combining the switching action of multiple pass gates, the circuit achieves sufficient drive strength to overcome the PMOS pull-up effect at low voltages. This merging approach provides the necessary reliability for write operations while confining the increased complexity to the dedicated low-voltage path.
3Reliability
If the third inverter is powered between a floating node and reference node, then the pass gates can pull outputs low successfully, but the circuit design becomes more complex
Solution Approach 1:
The patent introduces a floating node as an intermediary power supply for the third inverter in the low-voltage write replica path. This floating node acts as a mediator that enables the inverter to operate with enhanced pull-down capability while maintaining compatibility with low-voltage operation. The floating node configuration allows the pass gates to effectively pull the output low by providing an intermediate reference that facilitates the switching action against the PMOS pull-up.
Data Source
AI summary
Disclosed herein is an electronic device including a bit line and a complementary bit line, first and second cross coupled inverters, a first pass gate coupled between the complementary bit line and the first inverter, and a second pass gate coupled between the bit line and the second inverter. The electronic device also includes third and fourth cross coupled inverters, a third pass gate coupled between the complementary bit line and the third inverter, and a fourth pass gate coupled between the bit line and the fourth inverter. The first, second, and fourth inverters are powered between a supply node and a reference node, and the third inverter is powered between a floating node and the reference node. The first pass gate and third pass gate are coupled in parallel.