Tiled Power Module Chip and Passive Element Layout
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Solution Overview
Problem
Existing power modules face challenges in achieving high power density and efficient heat dissipation due to their stacked structure, which limits their height and results in asymmetric heat dissipation performance, affecting current and power output capabilities, especially in space-constrained environments like data centers and mobile devices.
Innovation Solution
A power module design where a chip and a passive element are tiled without overlapping projections on the pin-out surface, with the chip positioned vertically to reduce current impedance and parasitic inductance, and connection pins are arranged to ensure direct electrical connections, allowing for a compact footprint and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a chip and passive element are stacked vertically, then the footprint area is reduced, but the height increases and heat dissipation symmetry deteriorates
Solution Approach 1:
The patent transitions from a vertical stacked arrangement to a tiled arrangement where the chip and passive element are positioned side-by-side in the horizontal plane. This dimensional change allows both components to occupy the same vertical level, reducing the overall height while maintaining a compact footprint through efficient planar space utilization.
2Area of stationary object
If a chip and passive element are stacked vertically, then the footprint area is reduced, but heat dissipation symmetry deteriorates
Solution Approach 1:
The patent employs asymmetric thermal management by providing separate heat dissipation paths for the chip and passive element. The chip has dedicated heat dissipation structures on its bottom surface, while the passive element has its own heat dissipation structures, allowing each component to dissipate heat independently and symmetrically rather than relying on a shared vertical path.
3Reliability
If the chip is positioned vertically with terminal-out surface, then current impedance and parasitic inductance are reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary positioning and electrical connection establishment during the tiling assembly process. The chip is pre-oriented with its terminal-out surface facing the passive element, and electrical connections are established through direct contact or conductive structures before final module assembly, simplifying subsequent manufacturing steps.
Data Source
AI summary
The present disclosure provides a power module and a method for manufacturing the power module. The power module includes a chip, a passive element and connection pins. The connection pins are provided on a pin-out surface of the power module, and are electrically connected to at least one of a chip terminal of the chip and the passive element; a projection of the chip on the pin-out surface of the power module does not overlap with a projection of the passive element on the pin-out surface of the power module, and an angle between the terminal-out surface of the chip and the pin-out surface of the power module is greater than 45° and less than 135°.