FDSOI SRAM Cell Bias Voltage Control for Threshold Matching
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Solution Overview
Problem
SRAM memory cells on FDSOI technology face challenges in minimizing operating voltage, which directly affects power consumption, as existing methods struggle to balance threshold voltages of PMOS and NMOS transistors, leading to inefficiencies in read and write operations.
Innovation Solution
A method that adjusts the bias voltage of a shared doped well in an SRAM cell formed by FDSOI-type NMOS and PMOS transistors, ensuring the threshold voltages of both types of transistors are equal within a 10% margin, and temperature-compensates the bias voltage to maintain optimal operating conditions, thereby minimizing the operating voltage while preventing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the operating voltage Vdd is reduced to decrease power consumption, then power consumption decreases, but the risk of errors during read and write operations increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bias voltage of the doped well to compensate for threshold voltage variations. By modifying the bias voltage parameter in response to temperature and manufacturing variations, the system maintains optimal transistor matching without requiring high operating voltages, thus reducing power consumption while preventing read/write errors
Solution Approach 2:
The patent implements feedback mechanisms through temperature sensing and bias voltage adjustment. The system continuously monitors temperature and adjusts the well bias voltage accordingly to maintain stable threshold voltage matching. This feedback loop ensures that operating voltage can be minimized while maintaining reliability across varying conditions
2Use of energy by moving object
If the threshold voltages of PMOS and NMOS transistors are made equal to minimize operating voltage, then operating voltage decreases, but manufacturing dispersions and temperature variations cause threshold voltage mismatches
Solution Approach 1:
The patent applies local quality by creating a doped well with specific local properties (P-type doping) that affects the threshold voltages of transistors formed above it. By controlling the doping concentration and spatial distribution in the well, the system achieves localized threshold voltage adjustment to compensate for manufacturing dispersions and achieve better matching between PMOS and NMOS transistors
Solution Approach 2:
The patent uses parameter changes by adjusting the bias voltage applied to the doped well to compensate for threshold voltage mismatches caused by manufacturing variations and temperature changes. This dynamic parameter adjustment allows the system to maintain equal threshold voltages despite process variations, enabling lower operating voltage without sacrificing manufacturing precision
3Device complexity
If temperature variations are not compensated, then device complexity is reduced, but operating voltage increases due to threshold voltage drift
Solution Approach 1:
The patent applies parameter changes by adjusting the well bias voltage in response to temperature variations. As temperature changes cause threshold voltage drift, the system dynamically modifies the bias voltage parameter to compensate for this drift, maintaining stable operating conditions and preventing operating voltage increase without requiring complex temperature control hardware
Data Source
AI summary
An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.