III-V Material Etching in High Aspect Ratio FinFET Structures
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Solution Overview
Problem
Conventional methods for fabricating FinFETs face challenges such as selectively etching III-V materials like GaAs, InGaAs, and InP, reaching the bottom of high aspect ratio trenches, thermal budget limitations, and arsenic contamination during substrate processing.
Innovation Solution
A fin structure processing method involving selective etching and deposition of Group III-V semiconductor materials, with etching operations performed in the same chamber as deposition, using chlorine-containing gases like HCl, and incorporating chemical mechanical polishing to form features and openings between dielectric structures, while utilizing a substrate processing environment with integrated chamber abatement for arsenic removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used to remove III-V materials, then the etching process can be performed, but selective etching between III-V materials and Si/SiOx/SiNx becomes difficult
Solution Approach 1:
The patent changes the chemical parameters of the etching process by using chlorine-based etching gases (such as Cl2, BCl3, SiCl4) instead of conventional etchants. This parameter change enables selective etching of III-V materials while leaving Si, SiOx, and SiNx unaffected, thereby achieving the desired manufacturing precision without increasing process complexity
2Manufacturing precision
If high aspect ratio trenches are etched to reach the bottom, then the fin structure can be formed, but difficulty in reaching the bottom of the trenches occurs
Solution Approach 1:
The patent modifies the etching process parameters by using chlorine-based gases with specific flow rates and pressures optimized for high aspect ratio structures. The etching chemistry provides anisotropic etching characteristics that enable precise depth control and complete trench penetration, making the process as easy to operate as conventional methods while achieving the required manufacturing precision
3Productivity
If III-V materials are processed in conventional substrate processing environments, then deposition can be performed, but arsenic contamination occurs
Solution Approach 1:
The patent implements an inert atmosphere by using a closed chamber system with controlled gas flow during deposition. The chamber is purged with inert gases and maintained under vacuum or positive pressure with non-reactive gases, preventing arsenic contamination while maintaining high deposition efficiency. This creates an inert environment that protects the III-V materials from contamination
4Manufacturing precision
If multiple processing steps are performed in separate chambers, then each operation can be optimized, but thermal budget limitations arise
Solution Approach 1:
The patent combines multiple processing steps (etching and deposition operations) into a single chamber system. This merging allows sequential processing without removing the substrate from the temperature-controlled environment, thereby maintaining precise process control while avoiding thermal budget limitations that would occur with repeated heating and cooling cycles between separate chambers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the fabrication of FinFETs by enhancing the precision and control of III-V material processing, reducing arsenic contamination, and achieving effective etching of high aspect ratio structures, thereby improving the reliability and performance of semiconductor devices.
Implementation Method 1
performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures
Implementation Method 2
performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material
Implementation Method 3
planarizing the Group III-V semiconductor material by a chemical mechanical polishing process
Implementation Method 4
utilizing a substrate processing environment with integrated chamber abatement for arsenic removal
Data Source
AI summary
Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.