Trench Gate Semiconductor Device Channel Length Uniformity
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Solution Overview
Problem
Conventional methods for fabricating MOS transistors with trench gates result in non-uniform channel lengths across semiconductor wafers due to variations in trench depth, leading to performance issues like short channel effects and increased capacitance between the gate and drain.
Innovation Solution
A method involving a two-step etching process to form trenches with controlled depths, where a first trench is etched to a specific depth and then a second trench is formed with a recessed channel, allowing for a thicker gate insulating layer on the sidewall, which reduces channel length variation and capacitance between the gate and drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a one-step etching process is used to form the trench gate, then the manufacturing process is simple, but the channel length varies significantly across the wafer due to large trench depth differences between center and edge
Solution Approach 1:
The single etching process is segmented into two distinct etching steps: a first etching step that forms an initial trench structure, and a second etching step that completes the trench gate formation. This segmentation allows for better control of trench depth uniformity across the wafer, reducing channel length variation while maintaining manufacturing feasibility
Solution Approach 2:
The first etching step performs a preliminary action by forming an initial trench structure with controlled depth, creating a foundation that enables the second etching step to complete the trench gate with more uniform characteristics across the wafer surface
2Reliability
If the trench depth is increased to reduce short channel effect, then the gate control over the channel is improved, but the capacitance between gate and drain increases
Solution Approach 1:
The gate insulating layer is formed with different thicknesses at different locations: a first thickness at the bottom of the trench and a second (thicker) thickness at the sidewall. This local quality variation allows the trench gate to effectively control the channel (requiring sufficient gate-to-channel coupling) while the thicker sidewall insulation reduces the capacitive coupling between gate and drain regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of channel lengths, reducing short channel effects and gate-induced drain leakage, while ensuring uniformity and improving overall transistor performance.
Implementation Method 1
The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth
Implementation Method 2
Semiconductor substrate are doped with impurities through the first trench to form a doped region
Data Source
AI summary
A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.