3D Memory Inter-Tier Etch Stop Layer Precision
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Solution Overview
Problem
Current methods for manufacturing three-dimensional memory devices face challenges in effectively forming inter-tier memory openings and memory stack structures with precise etch stop layers, leading to inefficiencies in the fabrication process.
Innovation Solution
The method involves forming a first-tier alternating stack of insulating and spacer layers over a substrate, followed by a continuous etch stop material layer, and then performing anisotropic etch processes to create memory openings and fill structures, with the etch stop material layer providing selective etch resistance to form inter-tier memory openings and memory stack structures comprising memory films and vertical semiconductor channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a continuous etch stop material layer is formed over the first-tier alternating stack, then selective etching precision is improved, but device complexity increases
Solution Approach 1:
The etch stop function is segmented into two distinct material layers: a first etch stop material layer (silicon nitride) positioned between the first-tier and second-tier alternating stacks, and a second etch stop material layer (silicon oxide) positioned between the second-tier alternating stack and the inter-tier memory openings. This segmentation allows each layer to provide selective etch resistance for specific etching operations, improving overall etch precision while maintaining a systematic fabrication process.
2Manufacturing precision
If anisotropic etch processes are performed to form memory openings through multiple tiers, then manufacturing precision is improved, but processing time increases
Solution Approach 1:
The fabrication process employs periodic alternating etching operations: first forming first-tier memory openings through the first-tier alternating stack, then forming second-tier memory openings through the second-tier alternating stack, and finally forming inter-tier memory openings by removing sacrificial fill structures. Each etching cycle uses tailored anisotropic etch conditions optimized for specific depth ranges and material compositions, achieving high precision memory opening formation while managing overall processing time through systematic periodic action.
3Adaptability or versatility
If sacrificial memory opening fill structures are formed and subsequently removed, then inter-tier memory openings are enabled, but manufacturing steps increase
Solution Approach 1:
Sacrificial memory opening fill structures comprising silicon oxide and silicon nitride layers are formed in advance within the first-tier memory openings before second-tier alternating stack formation. These pre-positioned sacrificial structures serve as placeholders that define the future inter-tier memory opening locations and provide etch stop functions during subsequent processing. Their preliminary placement enables precise inter-tier structure formation while integrating the sacrificial function into the existing alternating stack architecture, minimizing additional manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the precise formation of inter-tier memory openings and memory stack structures, enhancing the fabrication efficiency and accuracy of three-dimensional memory devices by utilizing a distinct etch stop material layer for selective etching.
Implementation Method 1
performing a second anisotropic etch process that is selective to the etch stop material layer
Data Source
AI summary
A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop material layer, and the first-tier alternating stack, and memory opening fill structures each including a memory film and a vertical semiconductor channel located in the inter-tier memory openings. The material of the etch stop material layer is different from materials of the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.